LexDanaLexDanabeta
Inventor

Sean J. Treichler

Inventor
Mountain View, CA, US

Overview

54→
Patents
2003–2020
Patent span
Physics
Primary field (CPC G)

Patents· 54 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing44%
G06TImage data processing or generation, in general16%
G01RMeasuring electric variables6%
H04LTransmission of digital information, e.g. telegraphic communication6%
G05BControl or regulating systems in general5%
G16ZInformation and communication technology [ict] specially adapted for specific application fields, not otherwise provided for5%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h105%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses4%
G09GArrangements or circuits for control of indicating devices using static means to present variable information2%
G11CStatic stores2%
PatentTitleYear
10,795,722Compute task state encapsulation20209,921,873'Controlling work distribution for processing tasks'20189,891,949'System and method for runtime scheduling of GPU tasks'20189,442,759'Concurrent execution of independent streams in multi-channel time slice groups'20169,164,690'System, method, and computer program product for copying data between memory locations'20159,147,224'Method for handling state transitions in a network of virtual processing nodes'20159,098,383'Consolidated crossbar that supports a multitude of traffic types'20158,984,183'Signaling, ordering, and execution of dynamically generated tasks in a processing system'20158,976,185'Method for handling state transitions in a network of virtual processing nodes'20158,948,167'System and method for using domains to identify dependent and independent operations'20158,941,653'Order-preserving distributed rasterizer'20158,872,833'Integrated circuit configuration system and method'20148,788,996'System and method for configuring semiconductor functional circuits'20148,775,112'System and method for increasing die yield'20148,768,642'System and method for remotely configuring semiconductor functional circuits'20148,760,460'Hardware-managed virtual buffers using a shared memory for load distribution'20148,707,081'Memory clock slowdown'20148,587,581'Order-preserving distributed rasterizer'20138,547,993'Asynchronous interface for communicating between clock domains'20138,495,327'Memory device synchronization'20138,327,071'Interprocessor direct cache writes'20128,307,165'Sorting requests to the DRAM for high page locality'20128,249,819'Virtual binning'20128,237,705'Hierarchical processor array'20128,077,174'Hierarchical processor array'20118,060,765'Power estimation based on block activity'20118,041,841'Protocol and interface for source-synchronous digital link'20117,966,439'Apparatus, system, and method for a fast data return memory controller'20117,958,483'Clock throttling based on activity-level signals'20117,852,340'Scalable shader architecture'20107,836,318'Memory clock slowdown'20107,821,520'Fragment processor having dual mode register file'20107,809,782'Method and system for selecting a set of parameters'20107,747,915'System and method for improving the yield of integrated circuits containing memory'20107,746,349'Method and apparatus for display of data'20107,584,321'Memory address and datapath multiplexing'20097,562,205'Virtual address translation system with caching of variable-range translation clusters'20097,523,209'Protocol and interface for source-synchronous digital link'20097,478,289'System and method for improving the yield of integrated circuits containing memory'20097,406,546'Long-distance synchronous bus'20087,385,607'Scalable shader architecture'20087,334,108'Multi-client virtual address translation system with translation units of variable-range size'20087,287,145'System, apparatus and method for reclaiming memory holes in memory composed of identically-sized memory devices'20077,278,008'Virtual address translation system with caching of variable-range translation clusters'20077,275,143'System, apparatus and method for avoiding page conflicts by characterizing addresses in parallel with translations of memory addresses'20077,240,179'System, apparatus and method for reclaiming memory holes in memory composed of arbitrarily-sized memory devices'20077,187,220'Memory clock slowdown'20077,117,238'Method and system for performing pipelined reciprocal and reciprocal square root operations'20067,042,263'Memory clock slowdown synthesis circuit'20066,980,208'System and method for enhancing depth value processing in a graphics pipeline'20056,957,298'System and method for a high bandwidth-low latency memory controller'20056,779,069'Computer system with source-synchronous digital link'20046,724,395'System, method and article of manufacture for anisotropic texture sampling'20046,647,456'High bandwidth-low latency memory controller'2003

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2003–2020Patents assigned to NVIDIA CORP (54)· patent assignee history
2003–2005Based in Palo Alto, CA, US· patent location history
2004–2014Based in Mountain View, CA, US· patent location history
2004Based in Cupertino, CA, US· patent location history
2011–2020Patents assigned to TREICHLER SEAN J (18)· patent assignee history
2011–2015Patents assigned to KILGARIFF EMMETT M (6)· patent assignee history
2011–2014Patents assigned to MONTRYM JOHN S (6)· patent assignee history
2011–2020Based in Sunnyvale, CA, US· patent location history
2015–2020Patents assigned to SHAH LACKY V (7)· patent assignee history
2015Based in Sunnnyvale, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
NVIDIA CORP542003–2020
TREICHLER SEAN Jself182011–2020
SHAH LACKY V72015–2020
KILGARIFF EMMETT M62011–2015
MONTRYM JOHN S62011–2014
Locations
LocationPatentsSpan
Mountain View, California, US322004–2014
Sunnyvale, California, US182011–2020
Palo Alto, California, US22003–2005
Sunnnyvale, California, US12015
Cupertino, California, US12004