Inventor

Sampath Purushothaman

Inventor

Yorktown Heights, NY, US

Overview

1991–2020

Patent span

Electricity

Primary field (CPC H)

Patents· 186 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Wprimary

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1025%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1014%

H05KPrinted circuits10%

Y10TTechnical subjects covered by former us classification9%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests6%

H10DInorganic electric semiconductor devices5%

H01BCables3%

H01LSemiconductor devices3%

B82YSpecific uses or applications of nanostructures2%

C08GMacromolecular compounds obtained otherwise than by reactions only involving unsaturated carbon-to-carbon bonds2%

PatentTitleYear

10,796,9583D integration method using SOI substrates and structures produced thereby2020 10,777,4543D integration method using SOI substrates and structures produced thereby2020 10,767,084Enhanced adhesive materials and processes for 3D applications2020 10,651,0863D integration method using SOI substrates and structures produced thereby2020 10,340,182Enhanced via fill material and processing for dual damscene integration2019 9,994,741Enhanced adhesive materials and processes for 3D applications2018 9,412,620'Three-dimensional integrated circuit device fabrication including wafer scale membrane'2016 9,218,956'Capping coating for 3D integration applications'2015 9,111,925'Process for enhanced 3D integration and structures generated using the same'2015 9,089,080'Corrugated interfaces for multilayered interconnects'2015 9,064,717'Lock and key through-via method for wafer level 3D integration and structures produced thereby'2015 8,963,278'Three-dimensional integrated circuit device using a wafer scale membrane'2015 8,962,448'Computer readable medium encoded with a program for fabricating 3D integrated circuit device using interface wafer as permanent carrier'2015 8,927,087'Bonding of substrates including metal-dielectric patterns with metal raised above dielectric and structures so formed'2015 8,912,050'Capping coating for 3D integration applications'2014 8,901,741'Interconnect structures with engineered dielectrics with nanocolumnar porosity'2014 8,828,521'Corrugated interfaces for multilayered interconnects'2014 8,778,736'Capping coating for 3D integration applications'2014 8,738,167'3D integrated circuit device fabrication with precisely controllable substrate removal'2014 8,664,081'Method for fabricating 3D integrated circuit device using interface wafer as permanent carrier'2014 8,637,953'Wafer scale membrane for three-dimensional integrated circuit device fabrication'2014 8,629,553'3D integrated circuit device fabrication with precisely controllable substrate removal'2014 8,623,741'Homogeneous porous low dielectric constant materials'2014 8,617,689'Bonding of substrates including metal-dielectric patterns with metal raised above dielectric and structures so formed'2013 8,600,202'Process for enhanced 3D integration and structures generated using the same'2013 8,569,874'High memory density, high input/output bandwidth logic-memory structure and architecture'2013 8,563,396'3D integration method using SOI substrates and structures produced thereby'2013 8,525,144'Programmable via devices'2013 8,519,540'Self-aligned dual damascene BEOL structures with patternable low- K material and methods of forming same'2013 8,512,849'Corrugated interfaces for multilayered interconnects'2013 8,492,239'Homogeneous porous low dielectric constant materials'2013 8,492,869'3D integrated circuit device having lower-cost active circuitry layers stacked before higher-cost active circuitry layer'2013 8,491,987'Selectively coated self-aligned mask'2013 8,481,423'Methods to mitigate plasma damage in organosilicate dielectrics'2013 8,476,753'Process for enhanced 3D integration and structures generated using the same'2013 8,470,706'Methods to mitigate plasma damage in organosilicate dielectrics'2013 8,415,248'Self-aligned dual damascene BEOL structures with patternable low-k material and methods of forming same'2013 8,399,336'Method for fabricating a 3D integrated circuit device having lower-cost active circuitry layers stacked before higher-cost active circuitry layer'2013 8,389,967'Programmable via devices'2013 8,358,011'Interconnect structures with engineered dielectrics with nanocolumnar porosity'2013 8,343,868'Device and methodology for reducing effective dielectric constant in semiconductor devices'2013 8,338,952'Interconnect structures with ternary patterned features generated from two lithographic processes'2012 8,330,262'Processes for enhanced 3D integration and structures generated using the same'2012 8,314,005'Homogeneous porous low dielectric constant materials'2012 8,298,914'3D integrated circuit device fabrication using interface wafer as permanent carrier'2012 8,243,507'Programmable via devices in back end of line level'2012 8,241,995'Bonding of substrates including metal-dielectric patterns with metal raised above dielectric'2012 8,129,843'Methods to mitigate plasma damage in organosilicate dielectrics using a protective sidewall spacer'2012 8,129,256'3D integrated circuit device fabrication with precisely controllable substrate removal'2012 8,129,286'Reducing effective dielectric constant in semiconductor devices'2012 8,093,099'Lock and key through-via method for wafer level 3D integration and structures produced'2012 7,989,291'Anisotropic stress generation by stress-generating liners having a sublithographic width'2011 7,977,203'Programmable via devices with air gap isolation'2011 7,968,450'Methods for incorporating high dielectric materials for enhanced SRAM operation and structures produced thereby'2011 7,969,770'Programmable via devices in back end of line level'2011 7,947,907'Electronics structures using a sacrificial multi-layer hardmask scheme'2011 7,948,051'Nonlithographic method to produce self-aligned mask, articles produced by same and compositions for same'2011 7,944,055'Spin-on antireflective coating for integration of patternable dielectric materials and interconnect structures'2011 7,919,225'Photopatternable dielectric materials for BEOL applications and methods for use'2011 7,901,977'Data protection by detection of intrusion into electronic assemblies'2011 7,892,940'Device and methodology for reducing effective dielectric constant in semiconductor devices'2011 7,880,305'Technology for fabrication of packaging interface substrate wafers with fully metallized vias through the substrate wafer'2011 7,863,150'Method to generate airgaps with a template first scheme and a self aligned blockout mask'2011 7,855,101'Layer transfer process and functionally enhanced integrated circuits produced thereby'2010 7,855,455'Lock and key through-via method for wafer level 3 D integration and structures produced'2010 7,830,010'Surface treatment for selective metal cap applications'2010 7,811,923'Integrated wafer processing system for integration of patternable dielectric materials'2010 7,781,332'Methods to mitigate plasma damage in organosilicate dielectrics using a protective sidewall spacer'2010 7,750,479'Treatment of plasma damaged layer for critical dimension retention, pore sealing and repair'2010 7,709,370'Spin-on antireflective coating for integration of patternable dielectric materials and interconnect structures'2010 7,696,542'Anisotropic stress generation by stress-generating liners having a sublithographic width'2010 7,687,913'Recovery of hydrophobicity of low-k and ultra low-k organosilicate films used as inter metal dielectrics'2010 7,659,534'Programmable via devices with air gap isolation'2010 7,633,079'Programmable fuse/non-volatile memory structures in BEOL regions using externally heated phase change material'2009 7,592,685'Device and methodology for reducing effective dielectric constant in semiconductor devices'2009 7,545,671'Static random access memory cell with improved stability'2009 7,517,637'Method of producing self-aligned mask in conjunction with blocking mask, articles produced by same and composition for same'2009 7,485,341'Nonlithographic method to produce masks by selective reaction, articles produced, and composition for same'2009 7,467,742'Electrically conducting adhesives for via fill applications'2008 7,405,147'Device and methodology for reducing effective dielectric constant in semiconductor devices'2008 7,397,691'Static random access memory cell with improved stability'2008 7,393,776'Method of forming closed air gap interconnects and structures formed thereby'2008 7,371,684'Process for preparing electronics structures using a sacrificial multilayer hardmask scheme'2008 7,361,991'Closed air gap interconnect structure'2008 7,309,649'Method of forming closed air gap interconnects and structures formed thereby'2007 7,268,432'Interconnect structures with engineered dielectrics with nanocolumnar porosity'2007 7,179,758'Recovery of hydrophobicity of low-k and ultra low-k organosilicate films used as inter metal dielectrics'2007 7,098,476'Multilayer interconnect structure containing air gaps and method for making'2006 7,084,479'Line level air gaps'2006 7,045,453'Very low effective dielectric constant interconnect structures and methods for fabricating the same'2006 7,037,744'Method for fabricating a self-aligned nanocolumnar airbridge and structure produced thereby'2006 7,030,495'Method for fabricating a self-aligned nanocolumnar airbridge and structure produced thereby'2006 7,030,481'High density chip carrier with integrated passive devices'2006 7,023,093'Very low effective dielectric constant interconnect Structures and methods for fabricating the same'2006 6,962,872'High density chip carrier with integrated passive devices'2005 6,943,451'Semiconductor devices containing a discontinuous cap layer and methods for forming same'2005 6,930,034'Robust ultra-low k interconnect structures using bridge-then-metallization fabrication sequence'2005 6,911,400'Nonlithographic method to produce self-aligned mask, articles produced by same and compositions for same'2005 6,831,366'Interconnects containing first and second porous low-k dielectrics separated by a porous buried etch stop layer'2004 6,831,364'Method for forming a porous dielectric material layer in a semiconductor device and device formed'2004 6,819,000'High density area array solder microjoining interconnect structure and fabrication method'2004 6,815,329'Multilayer interconnect structure containing air gaps and method for making'2004 6,784,485'Diffusion barrier layer and semiconductor device containing same'2004 6,780,499'Ordered two-phase dielectric film, and semiconductor device containing the same'2004 6,759,321'Stabilization of fluorine-containing low-k dielectrics in a metal/insulator wiring structure by ultraviolet irradiation'2004 6,747,472'Temporary device attach structure for test and burn in of microjoint interconnects and method for fabricating the same'2004 6,737,725'Multilevel interconnect structure containing air gaps and method for making'2004 6,732,908'High density raised stud microjoining system and methods of fabricating the same'2004 6,726,996'Laminated diffusion barrier'2004 6,724,069'Spin-on cap layer, and semiconductor device containing same'2004 6,720,249'Protective hardmask for producing interconnect structures'2004 6,716,742'Low-k interconnect structure comprised of a multilayer of spin-on porous dielectrics'2004 6,710,450'Interconnect structure with precise conductor resistance and method to form same'2004 6,682,786'Liquid crystal display cell having liquid crystal molecules in vertical or substantially vertical alignment'2004 6,678,949'Process for forming a multi-level thin-film electronic packaging structure'2004 6,677,680'Hybrid low-k interconnect structure comprised of 2 spin-on dielectric materials'2004 6,661,098'High density area array solder microjoining interconnect structure and fabrication method'2003 6,657,305'Semiconductor recessed mask interconnect technology'2003 6,646,355'Structure comprising beam leads bonded with electrically conductive adhesive'2003 6,641,899'Nonlithographic method to produce masks by selective reaction, articles produced, and composition for same'2003 6,632,314'Method of making a lamination and surface planarization for multilayer thin film interconnect'2003 6,603,204'Low-k interconnect structure comprised of a multilayer of spin-on porous dielectrics'2003 6,583,847'Self alignment of substrates by magnetic alignment'2003 6,577,011'Chip interconnect wiring structure with low dielectric constant insulator and methods for fabricating the same'2003 6,569,707'Method for improving performance of organic semiconductors in bottom electrode structure'2003 6,555,762'Electronic package having substrate with electrically conductive through holes filled with polymer and conductive composition'2003 6,537,908'Method for dual-damascence patterning of low-k interconnects using spin-on distributed hardmask'2003 6,500,604'Method for patterning sensitive organic thin films'2002 6,451,712'Method for forming a porous dielectric material layer in a semiconductor device and device formed'2002 6,448,655'Stabilization of fluorine-containing low-k dielectrics in a metal/insulator wiring structure by ultraviolet irradiation'2002 6,413,852'Method of forming multilevel interconnect structure containing air gaps including utilizing both sacrificial and placeholder material'2002 6,344,660'Thin-film field-effect transistor with organic semiconductor requiring low operating voltages'2002 6,337,522'Structure employing electrically conductive adhesives'2002 6,335,539'Method for improving performance of organic semiconductors in bottom electrode structure'2002 6,322,685'Apparatus and method for plating coatings on to fine powder materials and use of the powder therefrom'2001 6,300,164'Structure, materials, and methods for socketable ball grid'2001 6,297,559'Structure, materials, and applications of ball grid array interconnections'2001 6,281,452'Multi-level thin-film electronic packaging structure and related method'2001 6,255,671'Metal embedded passivation layer structure for microelectronic interconnect formation, customization and repair'2001 6,238,599'High conductivity, high strength, lead-free, low cost, electrically conducting materials and applications'2001 6,224,690'Flip-Chip interconnections using lead-free solders'2001 6,207,472'Low temperature thin film transistor fabrication'2001 6,203,926'Corrosion-free multi-layer conductor'2001 6,184,121'Chip interconnect wiring structure with low dielectric constant insulator and methods for fabricating the same'2001 6,177,975'Precision alignment of plates'2001 6,120,885'Structure, materials, and methods for socketable ball grid'2000 6,114,413'Thermally conducting materials and applications for microelectronic packaging'2000 6,104,466'Precision alignment of plates'2000 6,061,114'Alignment of liquid crystal layers'2000 6,059,952'Method of fabricating coated powder materials and their use for high conductivity paste applications'2000 6,020,946'Dry processing for liquid-crystal displays using low energy ion bombardment'2000 6,015,509'Composition containing a polymer and conductive filler and use thereof'2000 5,997,773'Method for providing discharge protection or shielding'1999 5,985,458'Housing for electromagnetic interference shielding'1999 5,981,970'Thin-film field-effect transistor with organic semiconductor requiring low operating voltages'1999 5,958,590'Dendritic powder materials for high conductivity paste applications'1999 5,946,551'Fabrication of thin film effect transistor comprising an organic semiconductor and chemical solution deposited metal oxide gate dielectric'1999 5,922,466'Composite comprising a metal substrate and a corrosion protecting layer'1999 5,916,486'Method for providing discharge protection or shielding'1999 5,855,993'Electronic devices having metallurgies containing copper-semiconductor compounds'1999 5,837,119'Methods of fabricating dendritic powder materials for high conductivity paste applications'1998 5,830,332'Sputter deposition of hydrogenated amorphous carbon film and applications thereof'1998 5,776,587'Electronic package comprising a substrate and a semiconductor device bonded thereto'1998 5,700,398'Composition containing a polymer and conductive filler and use thereof'1997 5,633,047'Electronic devices having metallurgies containing copper-semiconductor compounds'1997 5,599,582'Adhesive layer in multi-level packaging and organic material as a metal diffusion barrier'1997 5,582,858'Adhesive layer in multi-level packaging and organic material as a metal diffusion barrier'1996 5,569,739'Adhesive layer in multi-level packaging and organic material as a metal diffusion barrier'1996 5,569,501'Diamond-like carbon films from a hydrocarbon helium plasma'1996 5,534,094'Method for fabricating multi-layer thin film structure having a separation layer'1996 5,532,031'I/O pad adhesion layer for a ceramic substrate'1996 5,491,610'Electronic package having active means to maintain its operating temperature constant'1996 5,483,105'Module input-output pad having stepped set-back'1996 5,470,661'Diamond-like carbon films from a hydrocarbon helium plasma'1995 5,436,412'Interconnect structure having improved metallization'1995 5,427,983'Process for corrosion free multi-layer metal conductors'1995 5,420,073'Structure and method for a superbarrier to prevent diffusion between a noble and a non-noble metal'1995 5,367,195'Structure and method for a superbarrier to prevent diffusion between a noble and a non-noble metal'1994 5,326,643'Adhesive layer in multi-level packaging and organic material as a metal diffusion barrier'1994 5,304,284'Methods for etching a less reactive material in the presence of a more reactive material'1994 5,296,189'Method for producing metal powder with a uniform distribution of dispersants, method of uses thereof and structures fabricated therewith'1994 5,258,236'Multi-layer thin film structure and parallel processing method for fabricating same'1993 5,167,913'Method of forming an adherent layer of metallurgy on a ceramic substrate'1992 5,074,969'Composition and coating to prevent current induced electrochemical dendrite formation between conductors on dielectric substrate'1991 5,038,195'Composition and coating to prevent current induced electrochemical dendrite formation between conductors on dielectric substrate'1991 4,985,310'Multilayered metallurgical structure for an electronic component'1991

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1991–2020Patents assigned to IBM (182)· patent assignee history

1991–2020Based in Yorktown Heights, NY, US· patent location history

2011–2020Patents assigned to PURUSHOTHAMAN SAMPATH (41)· patent assignee history

2012–2020Patents assigned to YU ROY R (14)· patent assignee history

2012–2015Patents assigned to FAROOQ MUKTA G (8)· patent assignee history

2012–2015Patents assigned to HANNON ROBERT (8)· patent assignee history

2012–2020Based in Armonk, NY, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
IBM	182	1991–2020
PURUSHOTHAMAN SAMPATHself	41	2011–2020
YU ROY R	14	2012–2020
FAROOQ MUKTA G	8	2012–2015
HANNON ROBERT	8	2012–2015

Locations

Location	Patents	Span
Yorktown Heights, New York, US	175	1991–2020
Armonk, New York, US	11	2012–2020