Inventor
Christopher M. Prindle
Inventor
Poughkeepsie, NY, US
Overview
Patents· 20 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices31%
H01LSemiconductor devices28%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1021%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1016%
G06FElectric digital data processing3%
B82YSpecific uses or applications of nanostructures2%
PatentTitleYear
10,734,525Gate-all-around transistor with spacer support and methods of forming same202010,699,965Removal of epitaxy defects in transistors202010,388,770Gate and source/drain contact structures positioned above an active region of a transistor device201910,388,747Gate contact structure positioned above an active region with air gaps positioned adjacent the gate structure201910,290,738Methods of forming epi semiconductor material on a recessed fin in the source/drain regions of a FinFET device201910,170,544Integrated circuit products that include FinFET devices and a protection layer formed on an isolation region201910,068,978Methods, apparatus and system for providing source-drain epitaxy layer with lateral over-growth suppression20189,876,077Methods of forming a protection layer on an isolation region of IC products comprising FinFET devices20189,806,078'FinFET spacer formation on gate sidewalls, between the channel and source/drain regions'20179,685,384'Devices and methods of forming epi for aggressive gate pitch'20179,640,533'Methods, apparatus and system for providing source-drain epitaxy layer with lateral over-growth suppression'20179,496,354'Semiconductor devices with dummy gate structures partially on isolation regions'20169,236,452'Raised source/drain EPI with suppressed lateral EPI overgrowth'20169,230,802'Transistor(s) with different source/drain channel junction characteristics, and methods of fabrication'20169,184,263'Methods of forming gate structures for semiconductor devices using a replacement gate technique and the resulting devices'20159,147,748'Methods of forming replacement spacer structures on semiconductor devices'20158,748,302'Replacement gate approach for high-k metal gate stacks by using a multi-layer contact level'20148,735,236'High-k metal gate electrode structure formed by removing a work function on sidewalls in replacement gate technology'20147,601,641'Two step optical planarizing layer etch'20096,924,232'Semiconductor process and composition for forming a barrier material overlying copper'2005Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2005Patents assigned to FREESCALE SEMICONDUCTOR INC (1)· patent assignee history
2005Based in Crolles, FR· patent location history
2009Patents assigned to GLOBAL FOUNDRIES INC (1)· patent assignee history
2009–2020Based in Poughkeepsie, NY, US· patent location history
2014–2020Patents assigned to GLOBALFOUNDRIES INC (17)· patent assignee history
2014Patents assigned to GROSCHOPF JOHANNES F (1)· patent assignee history
2014Patents assigned to HEMPEL KLAUS (1)· patent assignee history
2014Based in Dresden, DE· patent location history
2017–2018Based in Poughkeppsie, NY, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| GLOBALFOUNDRIES INC | 17 | 2014–2020 |
| FREESCALE SEMICONDUCTOR INC | 1 | 2005 |
| GLOBAL FOUNDRIES INC | 1 | 2009 |
| GROSCHOPF JOHANNES F | 1 | 2014 |
| HEMPEL KLAUS | 1 | 2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Poughkeepsie, New York, US | 15 | 2009–2020 |
| Poughkeppsie, New York, US | 2 | 2017–2018 |
| Dresden, DE | 2 | 2014 |
| Crolles, FR | 1 | 2005 |