Inventor
Siva P. Adusumilli
Inventor
South Burlington, VT, US
Overview
Patents· 28 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices27%
H10DInorganic electric semiconductor devices22%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1018%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1018%
G02BOptical elements, systems or apparatus5%
G02FOptical devices or arrangements for the control of light by modification of the optical properties of the media of the elements involved therein2%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation2%
B82YSpecific uses or applications of nanostructures1%
C23CCoating metallic material1%
G06FElectric digital data processing1%
PatentTitleYear
11,127,816Heterojunction bipolar transistors with one or more sealed airgap202111,121,097Active x-ray attack prevention device202111,107,884Sealed cavity structures with a planar surface202111,081,561Field-effect transistors with vertically-serpentine gates202111,056,382Cavity formation within and under semiconductor devices202110,983,412Silicon photonic components fabricated using a bulk substrate202110,923,577Cavity structures under shallow trench isolation regions202110,909,443Neuromorphic circuit structure and method to form same202110,903,316Radio frequency switches with air gap structures202110,903,207Method of forming an integrated circuit (IC) with shallow trench isolation (STI) regions and the resulting IC structure202110,832,940Bulk substrates with a self-aligned buried polycrystalline layer202010,833,072Heterojunction bipolar transistors having bases with different elevations202010,833,183Interlayer ballistic transport semiconductor devices202010,818,763Field-effect transistors with laterally-serpentine gates202010,770,374Through-silicon vias for heterogeneous integration of semiconductor device structures202010,651,281Substrates with self-aligned buried dielectric and polycrystalline layers202010,580,893Sealed cavity structures with non-planar surface features to induce stress202010,466,514Electro-optic modulator with vertically-arranged optical paths201910,461,152Radio frequency switches with air gap structures201910,446,643Sealed cavity structures with a planar surface201910,411,107Semiconductor device with airgap spacer for transistor and related method201910,393,960Waveguides with multiple-level airgaps201910,263,013Method of forming an integrated circuit (IC) with hallow trench isolation (STI) regions and the resulting IC structure201910,217,846Vertical field effect transistor formation with critical dimension control201910,192,779Bulk substrates with a self-aligned buried polycrystalline layer201910,163,679Shallow trench isolation formation without planarization201810,156,676Waveguides with multiple airgaps arranged in and over a silicon-on-insulator substrate20189,984,936Methods of forming an isolated nano-sheet transistor device and the resulting device2018Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2018–2021Patents assigned to GLOBALFOUNDRIES INC (22)· patent assignee history
2018–2021Based in South Burlington, VT, US· patent location history
2019–2021Based in Burlington, VT, US· patent location history
2021Patents assigned to GLOBALFOUNDRIES US INC (7)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| GLOBALFOUNDRIES INC | 22 | 2018–2021 |
| GLOBALFOUNDRIES US INC | 7 | 2021 |
Locations
| Location | Patents | Span |
|---|---|---|
| South Burlington, VT, US | 22 | 2018–2021 |
| Burlington, VT, US | 6 | 2019–2021 |