Inventor
Michael Joseph Laramie
Inventor
Essex, VT, US
Overview
Patents· 6 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H03Kprimary
H03KPulse technique36%
G11CStatic stores29%
G06FElectric digital data processing21%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1014%
PatentTitleYear
6,054,873'Interconnect structure between heterogeneous core regions in a programmable array'20006,023,421'Selective connectivity between memory sub-arrays and a hierarchical bit line structure in a memory array'20006,005,410'Interconnect structure between heterogeneous core regions in a programmable array'19995,949,719'Field programmable memory array'19995,914,906'Field programmable memory array'19995,802,003'System for implementing write, initialization, and reset in a memory array using a single cell write port'1998Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1998–2000Patents assigned to IBM (6)· patent assignee history
1998–2000Based in Essex, VT, US· patent location history
1999–2000Based in Underhill, VT, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 6 | 1998–2000 |
Locations
| Location | Patents | Span |
|---|---|---|
| Essex, VT, US | 4 | 1998–2000 |
| Underhill, VT, US | 2 | 1999–2000 |