Inventor

Tahir Ghani

Inventor

Portland, OR, US

Overview

1998–2021

Patent span

Electricity

Primary field (CPC H)

Patents· 222 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary

H10DInorganic electric semiconductor devices28%

H01LSemiconductor devices26%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1015%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1012%

B82YSpecific uses or applications of nanostructures5%

H10BElectronic memory devices5%

H10NElectric solid-state devices not otherwise provided for3%

G11CStatic stores3%

H01FMagnets1%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests1%

PatentTitleYear

11,127,841Confined epitaxial regions for semiconductor devices and methods of fabricating semiconductor devices having confined epitaxial regions2021 11,121,073Through plate interconnect for a vertical MIM capacitor2021 11,121,030Transistors employing carbon-based etch stop layer for preserving source/drain material during contact trench etch2021 11,107,890FINFET transistor having a doped subfin structure to reduce channel to substrate leakage2021 11,101,356Doped insulator cap to reduce source/drain diffusion for germanium NMOS transistors2021 11,101,350Integrated circuit with germanium-rich channel transistors including one or more dopant diffusion barrier elements2021 11,101,268Transistors employing non-selective deposition of source/drain material2021 11,094,785Deuterium-based passivation of non-planar transistor interfaces2021 11,087,832Three-dimensional nanoribbon-based static random-access memory2021 11,081,570Transistors with lattice matched gate structure2021 11,069,795Transistors with channel and sub-channel regions with distinct compositions and dimensions2021 11,063,133Fin cut and fin trim isolation for advanced integrated circuit structure fabrication2021 11,056,492Dense memory arrays utilizing access transistors with back-side contacts2021 11,056,592Silicon substrate modification to enable formation of thin, relaxed, germanium-based layer2021 11,049,773Art trench spacers to enable fin release for non-lattice matched channels2021 11,043,492Self-aligned gate edge trigate and finFET devices2021 11,031,487Contact over active gate structures for advanced integrated circuit structure fabrication2021 11,024,713Gradient doping to lower leakage in low band gap material devices2021 11,018,264Three-dimensional nanoribbon-based logic2021 11,011,550Self-aligned top-gated non-planar oxide semiconductor thin film transistors2021 11,004,982Gate for a transistor2021 11,004,739Gate contact structure over active gate and method to fabricate same2021 11,004,954Epitaxial buffer to reduce sub-channel leakage in MOS transistors2021 10,985,267Fin trim isolation with single gate spacing for advanced integrated circuit structure fabrication2021 10,985,184Fins for metal oxide semiconductor device structures2021 10,985,263Thin film cap to lower leakage in low band gap material devices2021 10,978,568Passivation of transistor channel region interfaces2021 10,964,697Non-planar semiconductor device having doped sub-fin region and method to fabricate same2021 10,957,769High-mobility field effect transistors with wide bandgap fin cladding2021 10,957,796Semiconductor device having doped epitaxial region and its methods of fabrication2021 10,930,738Sub-fin leakage control in semicondcutor devices2021 10,930,557Self-aligned contacts2021 10,930,753Trench isolation for advanced integrated circuit structure fabrication2021 10,930,679Thin film transistors with a crystalline oxide semiconductor source/drain2021 10,910,265Gate aligned contact and method to fabricate same2021 10,903,364Semiconductor device with released source and drain2021 10,896,963Semiconductor device contacts with increased contact area2021 10,892,335Device isolation by fixed charge2021 10,886,408Group III-V material transistors employing nitride-based dopant diffusion barrier layer2021 10,886,272Techniques for forming dual-strain fins for co-integrated n-MOS and p-MOS devices2021 10,886,217Integrated circuit device with back-side interconnection to deep source/drain semiconductor2021 10,879,365Transistors with non-vertical gates2020 10,879,241Techniques for controlling transistor sub-fin leakage2020 10,879,353Selective germanium P-contact metalization through trench2020 10,868,233Approaches for strain engineering of perpendicular magnetic tunnel junctions (pMTJs) and the resulting structures2020 10,861,851Wrap-around trench contact structure and methods of fabrication2020 10,854,752High mobility strained channels for fin-based NMOS transistors2020 10,847,635Vertical integration scheme and circuit elements architecture for area scaling of semiconductor devices2020 10,847,714PSTTM device with multi-layered filter stack2020 10,847,631Gate-all-around (GAA) transistors with nanowires on an isolation pedestal2020 10,818,793Indium-rich NMOS transistor channels2020 10,811,595Techniques for forming logic including integrated spin-transfer torque magnetoresistive random-access memory2020 10,804,460Device, system and method for improved magnetic anisotropy of a magnetic tunnel junction2020 10,804,357Integration methods to fabricate internal spacers for nanowire devices2020 10,797,150Differential work function between gate stack metals to reduce parasitic capacitance2020 10,790,354Self-aligned gate edge and local interconnect2020 10,777,656Fin cut and fin trim isolation for advanced integrated circuit structure fabrication2020 10,770,651Perpendicular spin transfer torque memory (PSTTM) devices with enhanced perpendicular anisotropy and methods to form same2020 10,770,458Nanowire transistor device architectures2020 10,770,593Beaded fin transistor2020 10,755,984Replacement channel etch for high quality interface2020 10,756,204Fin trim isolation with single gate spacing for advanced integrated circuit structure fabrication2020 10,748,900Fin-based III-V/SI or GE CMOS SAGE integration2020 10,749,032Techniques for forming transistors including group III-V material nanowires using sacrificial group IV material layers2020 10,732,217Ferromagnetic resonance testing of buried magnetic layers of whole wafer2020 10,700,178Contact resistance reduction employing germanium overlayer pre-contact metalization2020 10,692,974Deuterium-based passivation of non-planar transistor interfaces2020 10,692,973Germanium-rich channel transistors including one or more dopant diffusion barrier elements2020 10,651,288Pseudomorphic InGaAs on GaAs for gate-all-around transistors2020 10,644,112Systems, methods and devices for isolation for subfin leakage2020 10,644,064Logic chip including embedded magnetic tunnel junctions2020 10,644,137III-V finfet transistor with V-groove S/D profile for improved access resistance2020 10,636,912FINFET transistor having a tapered subfin structure2020 10,636,960Strained perpendicular magnetic tunnel junction devices2020 10,629,483Self-aligned contacts2020 10,622,359Non-planar semiconductor device having doped sub-fin region and method to fabricate same2020 10,615,265Gate cut and fin trim isolation for advanced integrated circuit structure fabrication2020 10,607,884Gate aligned contact and method to fabricate same2020 10,586,848Apparatus and methods to create an active channel having indium rich side and bottom surfaces2020 10,580,860Integration methods to fabricate internal spacers for nanowire devices2020 10,580,970PSTTM device with free magnetic layers coupled through a metal layer having high temperature stability2020 10,580,865Transistor with a sub-fin dielectric region under a gate2020 10,573,747Multi-threshold voltage devices and associated techniques and configurations2020 10,559,744Texture breaking layer to decouple bottom electrode from PMTJ device2020 10,559,683Apparatus and methods to create a buffer to reduce leakage in microelectronic transistors2020 10,553,680Selective germanium P-contact metalization through trench2020 10,546,858Low damage self-aligned amphoteric FINFET tip doping2020 10,541,334Techniques for integration of Ge-rich p-MOS source/drain2020 10,541,316Contact over active gate structures for advanced integrated circuit structure fabrication2020 10,529,808Dopant diffusion barrier for source/drain to curb dopant atom diffusion2020 10,510,848Sub-fin sidewall passivation in replacement channel FinFETS2019 10,497,814III-V semiconductor alloys for use in the subfin of non-planar semiconductor devices and methods of forming the same2019 10,483,353Transistor including tensile-strained germanium channel2019 10,460,993Fin cut and fin trim isolation for advanced integrated circuit structure fabrication2019 10,461,082Well-based integration of heteroepitaxial N-type transistors with P-type transistors2019 10,461,193Apparatus and methods to create a buffer which extends into a gated region of a transistor2019 10,461,177Confined epitaxial regions for semiconductor devices and methods of fabricating semiconductor devices having confined epitaxial regions2019 10,446,685High-electron-mobility transistors with heterojunction dopant diffusion barrier2019 10,431,690High electron mobility transistors with localized sub-fin isolation2019 10,424,580Semiconductor devices having modulated nanowire counts2019 10,418,464Techniques for forming transistors on the same die with varied channel materials2019 10,418,415Interconnect capping process for integration of MRAM devices and the resulting structures2019 10,411,068Electrical contacts for magnetoresistive random access memory devices2019 10,411,007High mobility field effect transistors with a band-offset semiconductor source/drain spacer2019 10,403,752Prevention of subchannel leakage current in a semiconductor device with a fin structure2019 10,396,079Non-planar semiconductor device having doped sub-fin region and method to fabricate same2019 10,388,764High-electron-mobility transistors with counter-doped dopant diffusion barrier2019 10,388,800Thin film transistor with gate stack on multiple sides2019 10,373,977Transistor fin formation via cladding on sacrificial core2019 10,340,374High mobility field effect transistors with a retrograded semiconductor source/drain2019 10,340,445PSTTM device with bottom electrode interface material2019 10,340,185Gate aligned contact and method to fabricate same2019 10,326,075PSTTM device with multi-layered filter stack2019 10,319,812Self-aligned gate edge and local interconnect and method to fabricate same2019 10,304,946Vertical integration scheme and circuit elements architecture for area scaling of semiconductor devices2019 10,304,927Selective germanium p-contact metalization through trench2019 10,304,940Gate cut and fin trim isolation for advanced integrated circuit structure fabrication2019 10,297,670Contact resistance reduction employing germanium overlayer pre-contact metalization2019 10,290,709Apparatus and methods to create an indium gallium arsenide active channel having indium rich surfaces2019 10,283,589Integration methods to fabricate internal spacers for nanowire devices2019 10,263,036Strain assisted spin torque switching spin transfer torque memory2019 10,243,078Carrier confinement for high mobility channel devices2019 10,229,997Indium-rich NMOS transistor channels2019 10,229,981Gate-all-around (GAA) transistor with stacked nanowires on locally isolated substrate2019 10,211,208High-mobility semiconductor source/drain spacer2019 10,192,783Gate contact structure over active gate and method to fabricate same2019 10,170,314Pulsed laser anneal process for transistor with partial melt of a raised source-drain2019 10,153,372High mobility strained channels for fin-based NMOS transistors2018 10,147,817Techniques for integration of Ge-rich p-MOS source/drain2018 10,141,226Self-aligned contacts2018 10,121,856Integration methods to fabricate internal spacers for nanowire devices2018 10,109,711CMOS FinFET device having strained SiGe fins and a strained Si cladding layer on the NMOS channel2018 10,084,043High mobility nanowire fin channel on silicon substrate formed using sacrificial sub-fin2018 10,074,573CMOS nanowire structure2018 10,056,380Non-planar semiconductor device having doped sub-fin region and method to fabricate same2018 10,026,829Semiconductor device with isolated body portion2018 9,997,563Logic chip including embedded magnetic tunnel junctions2018 9,935,107CMOS FinFET device with dual strained cladding layers on relaxed SiGe fins, and method of fabricating the same2018 9,929,273'Apparatus and methods of forming fin structures with asymmetric profile'2018 9,923,054'Fin structure having hard mask etch stop layers underneath gate sidewall spacers'2018 9,892,967'Self-aligned contacts'2018 9,893,149'High mobility strained channels for fin-based transistors'2018 9,882,027'Confined epitaxial regions for semiconductor devices and methods of fabricating semiconductor devices having confined epitaxial regions'2018 9,876,016Wrap-around trench contact structure and methods of fabrication2018 9,859,368'Integration methods to fabricate internal spacers for nanowire devices'2018 9,859,424'Techniques for integration of Ge-rich p-MOS source/drain contacts'2018 9,831,306Self-aligned gate edge and local interconnect and method to fabricate same2017 9,761,713'Multi-threshold voltage devices and associated techniques and configurations'2017 9,754,940'Self-aligned contact metallization for reduced contact resistance'2017 9,735,270'Semiconductor transistor having a stressed channel'2017 9,728,464'Self-aligned 3-D epitaxial structures for MOS device fabrication'2017 9,722,023'Selective germanium P-contact metalization through trench'2017 9,716,037'Gate aligned contact and method to fabricate same'2017 9,705,000'III-V layers for n-type and p-type MOS source-drain contacts'2017 9,680,013'Non-planar device having uniaxially strained semiconductor body and method of making same'2017 9,660,181'Logic chip including embedded magnetic tunnel junctions'2017 9,627,384'Transistors with high concentration of boron doped germanium'2017 9,607,987'Methods for forming fins for metal oxide semiconductor device structures'2017 9,608,059'Semiconductor device with isolated body portion'2017 9,583,491'CMOS nanowire structure'2017 9,577,057'Semiconductor device contacts'2017 9,508,821'Self-aligned contacts'2016 9,490,364'Semiconductor transistor having a stressed channel'2016 9,484,272'Methods for fabricating strained gate-all-around semiconductor devices by fin oxidation using an undercut etch-stop layer'2016 9,484,432'Contact resistance reduction employing germanium overlayer pre-contact metalization'2016 9,484,447'Integration methods to fabricate internal spacers for nanowire devices'2016 9,466,565'Self-aligned contacts'2016 9,461,143'Gate contact structure over active gate and method to fabricate same'2016 9,443,980'Pulsed laser anneal process for transistors with partial melt of a raised source-drain'2016 9,397,102'III-V layers for N-type and P-type MOS source-drain contacts'2016 9,349,810'Selective germanium P-contact metalization through trench'2016 9,240,322'Method for forming superactive deactivation-resistant junction with laser anneal and multiple implants'2016 9,224,810'CMOS nanowire structure'2015 9,224,735'Self-aligned contact metallization for reduced contact resistance'2015 9,219,155'Multi-threshold voltage devices and associated techniques and configurations'2015 9,196,704'Selective laser annealing process for buried regions in a MOS device'2015 9,184,294'High mobility strained channels for fin-based transistors'2015 9,166,004'Semiconductor device contacts'2015 9,153,583'III-V layers for N-type and P-type MOS source-drain contacts'2015 9,117,791'Selective germanium P-contact metalization through trench'2015 9,093,513'Self-aligned contacts'2015 9,059,024'Self-aligned contact metallization for reduced contact resistance'2015 9,054,178'Self-aligned contacts'2015 9,048,260'Method of forming a semiconductor device with tall fins and using hard mask etch stops'2015 9,041,146'Logic chip including embedded magnetic tunnel junctions'2015 9,029,221'Semiconductor devices having three-dimensional bodies with modulated heights'2015 9,006,069'Pulsed laser anneal process for transistors with partial melt of a raised source-drain'2015 8,994,104'Contact resistance reduction employing germanium overlayer pre-contact metalization'2015 8,963,579'Spin torque magnetic integrated circuits and devices therefor'2015 8,901,537'Transistors with high concentration of boron doped germanium'2014 8,847,281'High mobility strained channels for fin-based transistors'2014 8,735,869'Strained gate-all-around semiconductor devices formed on globally or locally isolated substrates'2014 8,598,003'Semiconductor device having doped epitaxial region and its methods of fabrication'2013 8,558,279'Non-planar device having uniaxially strained semiconductor body and method of making same'2013 8,436,404'Self-aligned contacts'2013 8,313,999'Multi-gate semiconductor device with self-aligned epitaxial source and drain'2012 8,198,692'Spin torque magnetic integrated circuits and devices therefor'2012 8,063,460'Spin torque magnetic integrated circuits and devices therefor'2011 7,732,285'Semiconductor device having self-aligned epitaxial source and drain extensions'2010 7,492,017'Semiconductor transistor having a stressed channel'2009 7,402,872'Method for forming an integrated circuit'2008 7,226,824'Nitrogen controlled growth of dislocation loop in stress enhanced transistor'2007 7,211,872'Device having recessed spacers for improved salicide resistance on polysilicon gates'2007 7,187,057'Nitrogen controlled growth of dislocation loop in stress enhanced transistor'2007 6,885,084'Semiconductor transistor having a stressed channel'2005 6,861,318'Semiconductor transistor having a stressed channel'2005 6,800,887'Nitrogen controlled growth of dislocation loop in stress enhanced transistor'2004 6,777,760'Device with recessed thin and thick spacers for improved salicide resistance on polysilicon gates'2004 6,621,131'Semiconductor transistor having a stressed channel'2003 6,593,633'Method and device for improved salicide resistance on polysilicon gates'2003 6,521,964'Device having spacers for improved salicide resistance on polysilicon gates'2003 6,509,618'Device having thin first spacers and partially recessed thick second spacers for improved salicide resistance on polysilicon gates'2003 6,506,652'Method of recessing spacers to improved salicide resistance on polysilicon gates'2003 6,271,096'Method and device for improved salicide resistance on polysilicon gates'2001 6,268,254'Method and device for improved salicide resistance on polysilicon gates'2001 6,251,762'Method and device for improved salicide resistance on polysilicon gates'2001 6,235,598'Method of using thick first spacers to improve salicide resistance on polysilicon gates'2001 6,188,117'Method and device for improved salicide resistance on polysilicon gates'2001 6,121,100'Method of fabricating a MOS transistor with a raised source/drain extension'2000 6,096,610'Transistor suitable for high voltage circuit'2000 6,020,244'Channel dopant implantation with automatic compensation for variations in critical dimension'2000 5,798,552'Transistor suitable for high voltage circuit'1998

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1998–2021Patents assigned to INTEL CORP (222)· patent assignee history

1998–2007Based in Beaverton, OR, US· patent location history

2003–2021Based in Portland, OR, US· patent location history

2011–2020Patents assigned to GHANI TAHIR (35)· patent assignee history

2012–2017Patents assigned to MURTHY ANAND S (12)· patent assignee history

2012–2019Patents assigned to CAPPELLANI ANNALISA (9)· patent assignee history

2014–2017Patents assigned to GLASS GLENN A (9)· patent assignee history

2014–2015Based in Hillsboro, OR, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
INTEL CORP	222	1998–2021
GHANI TAHIRself	35	2011–2020
MURTHY ANAND S	12	2012–2017
CAPPELLANI ANNALISA	9	2012–2019
GLASS GLENN A	9	2014–2017

Locations

Location	Patents	Span
Portland, OR, US	205	2003–2021
Beaverton, OR, US	15	1998–2007
Hillsboro, OR, US	2	2014–2015