Inventor

Hou-Yu Chen

Inventor

Zhubei City, TW

Overview

2003–2020

Patent span

Electricity

Primary field (CPC H)

Patents· 43 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary

H10DInorganic electric semiconductor devices38%

H01LSemiconductor devices31%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1020%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h107%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests2%

B82YSpecific uses or applications of nanostructures1%

H10BElectronic memory devices1%

PatentTitleYear

10,854,599Semiconductor device and manufacturing method thereof2020 10,840,346Raised epitaxial LDD in MuGFETs and methods for forming the same2020 10,797,164FinFETs having epitaxial capping layer on fin and methods for forming the same2020 10,797,052Method and structure for FinFET devices2020 10,516,024Raised epitaxial LDD in MuGFETs and methods for forming the same2019 10,515,966Enhanced channel strain to reduce contact resistance in NMOS FET devices2019 10,276,568Semiconductor device and manufacturing method thereof2019 10,276,565Semiconductor device and manufacturing method thereof2019 10,157,924Method and structure for FinFET devices2018 10,109,742Semiconductor device including fin structures and manufacturing method thereof2018 10,056,383Enhanced channel strain to reduce contact resistance in NMOS FET devices2018 10,014,223Multi-gate devices with replaced-channels and methods for forming the same2018 9,947,658Semiconductor device and manufacturing method thereof2018 9,941,368Raised epitaxial LDD in MuGFETs and methods for forming the same2018 9,831,242Semiconductor device and manufacturing method thereof2017 9,704,755'Multi-gate device structure including a fin-embedded isolation region and methods thereof'2017 9,691,903'Semiconductor device and manufacturing method thereof'2017 9,653,581'Semiconductor device and method of making'2017 9,634,104'FinFET and method of fabricating the same'2017 9,607,838'Enhanced channel strain to reduce contact resistance in NMOS FET devices'2017 9,553,172'Method and structure for FinFET devices'2017 9,520,502'FinFETs having epitaxial capping layer on fin and methods for forming the same'2016 9,515,167'Raised epitaxial LDD in MuGFETs and methods for forming the same'2016 9,514,991'Method of manufacturing a FinFET device having a stepped profile'2016 9,431,397'Method for fabricating a multi-gate device'2016 9,425,313'Semiconductor device and manufacturing method thereof'2016 9,397,157'Multi-gate device structure including a fin-embedded isolation region and methods thereof'2016 9,252,271'Semiconductor device and method of making'2016 9,171,925'Multi-gate devices with replaced-channels and methods for forming the same'2015 9,166,044'Raised epitaxial LDD in MuGFETs'2015 9,166,053'FinFET device including a stepped profile structure'2015 9,123,564'Semiconductor device with conformal doping and method of making'2015 9,053,934'Finfet and method of fabricating the same'2015 9,000,536'Fin field effect transistor having a highly doped region'2015 8,956,931'Method for fabricating a multi-gate device'2015 8,659,032'FinFET and method of fabricating the same'2014 8,405,168'Nanowire fabrication method and semiconductor element using nanowire fabricated thereby'2013 8,048,747'Method of manufacturing embedded metal-oxide-nitride-oxide-silicon memory device'2011 7,943,986'Method for fabricating a body contact in a finfet structure and a device including the same'2011 7,244,640'Method for fabricating a body contact in a Finfet structure and a device including the same'2007 7,187,000'High performance tunneling-biased MOSFET and a process for its manufacture'2007 6,674,130'High performance PD SOI tunneling-biased MOSFET'2004 6,518,105'High performance PD SOI tunneling-biased MOSFET'2003

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2003–2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (14)· patent assignee history

2003–2004Based in Kaoshiung, TW· patent location history

2007–2011Based in Kaohsiung, TW· patent location history

2011–2013Patents assigned to NAT APPLIED RES LABORATORIES (2)· patent assignee history

2011–2020Based in Hsinchu, TW· patent location history

2013–2015Patents assigned to CHEN HOU-YU (3)· patent assignee history

2014–2015Patents assigned to YANG SHYH-HORNG (2)· patent assignee history

2014–2020Based in Zhubei City, TW· patent location history

2015–2020Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (27)· patent assignee history

2017–2020Based in Hsinchu County, TW· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
TAIWAN SEMICONDUCTOR MFG CO LTD	27	2015–2020
TAIWAN SEMICONDUCTOR MFG	14	2003–2016
CHEN HOU-YUself	3	2013–2015
NAT APPLIED RES LABORATORIES	2	2011–2013
YANG SHYH-HORNG	2	2014–2015

Locations

Location	Patents	Span
Zhubei City, TW	27	2014–2020
Hsinchu, TW	7	2011–2020
Hsinchu County, TW	3	2017–2020
Kaohsiung, TW	2	2007–2011
Kaoshiung, TW	2	2003–2004