Inventor
MIRNG-JI LII
Inventor
TW
Overview
Patents· 62 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices34%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1033%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1015%
H10DInorganic electric semiconductor devices5%
H10KOrganic electric solid-state devices2%
Y02PClimate change mitigation technologies in the production or processing of goods2%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices1%
H01FMagnets1%
H10BElectronic memory devices1%
H10HInorganic light-emitting semiconductor devices having potential barriers1%
PatentTitleYear
12,598,995Semiconductor device and method of forming same202612,581,935Stacked via structures and methods for forming the same202612,550,710Semiconductor die202612,538,836Seal ring structure in the peripheral of device dies and with zigzag patterns and method forming same202612,532,738Chip package structure with heat conductive layer202612,532,789Package structure with cavity substrate202612,525,556Semiconductor devices and methods of manufacture202612,519,055Stacking via configuration for advanced silicon node products and methods for forming the same202612,494,379Heterogeneous bonding structure and method forming same202512,482,766MIMcap corner structures in the keep-out zones of a semiconductor die and methods of forming the same202512,482,790Packages with stacked dies and methods of forming the same202512,476,211Semiconductor device202512,463,150Bonding structures in semiconductor packaged device and method of forming same202512,243,681Programmable inductor and methods of manufacture202512,237,320Package structure and method of forming the same202512,230,595Metal bumps and method forming same202512,136,644Process for tuning via profile in dielectric material202412,087,648Seal ring structure with zigzag patterns and method forming same202412,068,303Package structure202412,062,586Semiconductor device structure with magnetic element202412,051,632Semiconductor package structure and method for forming semiconductor package structure202412,027,435Packages including multiple encapsulated substrate blocks and overlapping redistribution structures202412,021,048Semiconductor device202412,009,327Semiconductor die202411,990,428Bonding structures in semiconductor packaged device and method of forming same202411,967,579Method for forming package structure with cavity substrate202411,961,944Semiconductor device and manufacturing method thereof202411,942,445Semiconductor device with conductive pad202411,908,818Semiconductor device202411,901,266Semiconductor device structure and method for forming the same202411,894,241Heterogeneous bonding structure and method forming same202411,855,058Package structure and method of forming the same202311,854,835Heterogeneous bonding structure and method forming same202311,848,270Chip structure and method for forming the same202311,842,935Method for forming a reconstructed package substrate comprising substrates blocks202311,824,026Connector structure and method of forming same202311,812,646Display device and manufacturing method thereof202311,756,731Programmable inductor202311,742,204Multi-layer structures and methods of forming202311,728,217Wafer level package structure and method of forming same202311,652,086Packages with stacked dies and methods of forming the same202311,631,621Semiconductor device structure with magnetic element202311,594,484Forming bonding structures by using template layer as templates202311,569,419Semiconductor device and manufacturing method thereof202311,532,692Process for tuning via profile in dielectric material202211,532,583Semiconductor structure and manufacturing method thereof202211,476,125Multi-die package with bridge layer202211,462,509Package structure with electronic device in cavity substrate and method for forming the same202211,450,588Method for forming chip package structure with heat conductive layer202211,417,610Post-passivation interconnect structure202211,393,771Bonding structures in semiconductor packaged device and method of forming same202211,342,291Semiconductor packages with crack preventing structure202211,315,896Conical-shaped or tier-shaped pillar connections202211,264,342Package on package structure and method for forming the same202211,244,919Package structure and method of fabricating the same202211,239,305Display device and manufacturing method thereof202211,222,859Semiconductor device structure with bonding pad and method for forming the same202211,211,261Package structures and methods for forming the same202111,177,228Semiconductor device and bump formation process202111,177,355Semiconductor structure and manufacturing method thereof202111,158,614Thermal performance structure for semiconductor packages and method of forming same202111,152,344Integrated circuit package and methods of forming same2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2026Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (62)· patent assignee history
2021–2026Based in TW· patent location history
2026Patents assigned to TAIWAN SEMICONDUCTOR MFG COMPANY LTD (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG CO LTD | 62 | 2021–2026 |
| TAIWAN SEMICONDUCTOR MFG COMPANY LTD | 1 | 2026 |
Locations
| Location | Patents | Span |
|---|---|---|
| TW | 62 | 2021–2026 |