Inventor
Linda Pei Ee Chua
Inventor
Singapore, SG
Overview
Patents· 125 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1056%
H01LSemiconductor devices19%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1017%
H10DInorganic electric semiconductor devices4%
H05KPrinted circuits2%
Y10TTechnical subjects covered by former us classification1%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation0%
PatentTitleYear
RE048408Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect2021RE048111Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect202010,388,584Semiconductor device and method of forming Fo-WLCSP with recessed interconnect area in peripheral region of semiconductor die201910,388,612Semiconductor device and method of forming electromagnetic (EM) shielding for LC circuits201910,043,733Integrated circuit packaging system and method of manufacture thereof20189,893,045'Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect'20189,824,975'Semiconductor device and method of forming stepped interconnect layer for stacked semiconductor die'20179,799,589'Integrated circuit packaging system with a grid array with a leadframe and method of manufacture thereof'20179,754,897'Semiconductor device and method of forming electromagnetic (EM) shielding for LC circuits'20179,679,881'Semiconductor device and method of forming cavity adjacent to sensitive region of semiconductor die using wafer-level underfill material'20179,620,480'Integrated circuit packaging system with unplated leadframe and method of manufacture thereof'20179,576,873'Integrated circuit packaging system with routable trace and method of manufacture thereof'20179,530,738'Semiconductor device and method of forming interconnect structure and mounting semiconductor die in recessed encapsulant'20169,449,932'Semiconductor device and method of forming base substrate with recesses for capturing bumped semiconductor die'20169,443,828'Semiconductor device and method of embedding thermally conductive layer in interconnect structure for heat dissipation'20169,431,331'Semiconductor device and method of forming penetrable film encapsulant around semiconductor die and interconnect structure'20169,368,423'Semiconductor device and method of using substrate with conductive posts and protective layers to form embedded sensor die package'20169,331,002'Semiconductor device and method of forming through vias with reflowed conductive material'20169,324,641'Integrated circuit packaging system with external interconnect and method of manufacture thereof'20169,324,584'Integrated circuit packaging system with transferable trace lead frame'20169,312,194'Integrated circuit packaging system with terminals and method of manufacture thereof'20169,305,873'Integrated circuit packaging system with electrical interface and method of manufacture thereof'20169,293,351'Integrated circuit packaging system with planarity control and method of manufacture thereof'20169,219,029'Integrated circuit packaging system with terminals and method of manufacture thereof'20159,190,349'Integrated circuit packaging system with leadframe and method of manufacture thereof'20159,177,901'Semiconductor device and method of stacking die on leadframe electrically connected by conductive pillars'20159,177,897'Integrated circuit packaging system with trace protection layer and method of manufacture thereof'20159,177,848'Semiconductor wafer having through-hole vias on saw streets with backside redistribution layer'20159,123,712'Leadframe system with warp control mechanism and method of manufacture thereof'20159,105,620'Integrated circuit packaging system with routable traces and method of manufacture thereof'20159,059,011'Exposed interconnect for a package on package system'20159,048,211'Semiconductor device and method of embedding thermally conductive layer in interconnect structure for heat dissipation'20158,987,064'Integrated circuit packaging system with molded grid-array mechanism and method of manufacture thereof'20158,963,309'Semiconductor package with penetrable encapsulant joining semiconductor die and method thereof'20158,962,393'Integrated circuit packaging system with heat shield and method of manufacture thereof'20158,963,320'Integrated circuit packaging system with thermal structures and method of manufacture thereof'20158,957,509'Integrated circuit packaging system with thermal emission and method of manufacture thereof'20158,946,870'Semiconductor device and method of forming stepped interconnect layer for stacked semiconductor die'20158,937,379'Integrated circuit packaging system with trenched leadframe and method of manufacture thereof'20158,878,361'Leadless package system having external contacts'20148,841,173'Integrated circuit packaging system with leadframe lead array routing and method of manufacture thereof'20148,823,182'Semiconductor device and method of forming interconnect structure and mounting semiconductor die in recessed encapsulant'20148,815,643'Method of fabricating semiconductor die with through-hole via on saw streets and through-hole via in active area of die'20148,802,500'Integrated circuit packaging system with leads and method of manufacture thereof'20148,802,501'Integrated circuit packaging system with island terminals and method of manufacture thereof'20148,791,556'Integrated circuit packaging system with routable circuitry and method of manufacture thereof'20148,759,159'Integrated circuit packaging system with electrical interface and method of manufacture thereof'20148,723,305'Semiconductor package having semiconductor die with internal vertical interconnect structure and method therefor'20148,669,654'Integrated circuit packaging system with die paddle and method of manufacture thereof'20148,658,470'Integrated circuit packaging system with formed interconnects and method of manufacture thereof'20148,633,063'Integrated circuit packaging system with pad connection and method of manufacture thereof'20148,629,567'Integrated circuit packaging system with contacts and method of manufacture thereof'20148,623,708'Integrated circuit packaging system with grid-array mechanism and method of manufacture thereof'20148,623,711'Integrated circuit packaging system with package-on-package and method of manufacture thereof'20148,592,950'Semiconductor device and method of forming through vias with reflowed conductive material'20138,574,960'Semiconductor device and method of forming cavity adjacent to sensitive region of semiconductor die using wafer-level underfill material'20138,575,769'Semiconductor device and method of embedding thermally conductive layer in interconnect structure for heat dissipation'20138,569,112'Integrated circuit packaging system with encapsulation and leadframe etching and method of manufacture thereof'20138,557,638'Integrated circuit packaging system with pad connection and method of manufacture thereof'20138,558,392'Semiconductor device and method of forming interconnect structure and mounting semiconductor die in recessed encapsulant'20138,546,193'Semiconductor device and method of forming penetrable film encapsulant around semiconductor die and interconnect structure'20138,546,195'Semiconductor package having semiconductor die with internal vertical interconnect structure and method therefor'20138,536,692'Mountable integrated circuit package system with mountable integrated circuit die'20138,525,325'Integrated circuit packaging system with leads and method of manufacture thereof'20138,519,518'Integrated circuit packaging system with lead encapsulation and method of manufacture thereof'20138,513,788'Integrated circuit packaging system with pad and method of manufacture thereof'20138,502,352'Semiconductor device with conductive vias between saw streets'20138,501,541'Semiconductor device and method of conforming conductive vias between insulating layers in saw streets'20138,492,201'Semiconductor device and method of forming through vias with reflowed conductive material'20138,492,204'Integrated circuit package-in-package system with wire-in-film encapsulant and method for manufacturing thereof'20138,476,772'Semiconductor device and method of forming base substrate with recesses for capturing bumped semiconductor die'20138,466,057'Integrated circuit packaging system with filled vias and method of manufacture thereof'20138,406,004'Integrated circuit packaging system and method of manufacture thereof'20138,389,330'Integrated circuit package system with package stand-off and method of manufacture thereof'20138,378,477'Integrated circuit packaging system with film encapsulation and method of manufacture thereof'20138,349,657'Semiconductor device and method of forming conductive pillars in recessed region of peripheral area around the device for electrical interconnection to other devices'20138,334,169'Integrated circuit packaging system and method of manufacture thereof'20128,283,205'Semiconductor device and method of forming stepped interconnect layer for stacked semiconductor die'20128,270,176'Exposed interconnect for a package on package system'20128,258,015'Integrated circuit package system with penetrable film adhesive'20128,247,268'Semiconductor wafer having through-hole vias on saw streets with backside redistribution layer'20128,237,252'Semiconductor device and method of embedding thermally conductive layer in interconnect structure for heat dissipation'20128,188,586'Mountable integrated circuit package system with mounting interconnects'20128,183,675'Integrated circuit package-on-package system with anti-mold flash feature'20128,169,058'Semiconductor device and method of stacking die on leadframe electrically connected by conductive pillars'20128,168,458'Semiconductor device and method of forming bond wires and stud bumps in recessed region of peripheral area around the device for electrical interconnection to other devices'20128,164,184'Semiconductor device and method of forming conductive pillars in recessed region of peripheral area around the device for electrical interconnection to other devices'20128,143,711'Integrated circuit package system with offset stacking and anti-flash structure'20128,143,098'Integrated circuit packaging system with interposer and method of manufacture thereof'20128,119,447'Integrated circuit packaging system with through via die having pedestal and recess and method of manufacture thereof'20128,110,913'Integrated circuit package system with integral inner lead and paddle'20128,097,490'Semiconductor device and method of forming stepped interconnect layer for stacked semiconductor die'20128,084,302'Semiconductor package having semiconductor die with internal vertical interconnect structure and method therefor'20118,084,849'Integrated circuit package system with offset stacking'20118,080,882'Semiconductor device and method of forming stepped-down RDL and recessed THV in peripheral region of the device'20118,063,477'Integrated circuit packaging system having asymmetric encapsulation structures and method of manufacture thereof'20118,049,314'Integrated circuit package system with insulator over circuitry'20118,030,136'Semiconductor device and method of conforming conductive vias between insulating layers in saw streets'20118,026,127'Integrated circuit package system with slotted die paddle and method of manufacture thereof'20118,021,923'Semiconductor package having through-hole vias on saw streets formed with partial saw'20118,017,521'Semiconductor package having through-hole vias on saw streets formed with partial saw'20118,017,501'Semiconductor package having through-hole vias on saw streets formed with partial saw'20118,003,445'Integrated circuit packaging system with z-interconnects having traces and method of manufacture thereof'20117,993,979'Leadless package system having external contacts'20117,994,624'Integrated circuit package system with adhesive segment spacer'20117,989,269'Semiconductor package with penetrable encapsulant joining semiconductor die and method thereof'20117,985,628'Integrated circuit package system with interconnect lock'20117,977,802'Integrated circuit packaging system with stacked die and method of manufacture thereof'20117,968,979'Integrated circuit package system with conformal shielding and method of manufacture thereof'20117,952,176'Integrated circuit packaging system and method of manufacture thereof'20117,948,066'Integrated circuit package system with lead locking structure'20117,923,846'Integrated circuit package-in-package system with wire-in-film encapsulant'20117,902,638'Semiconductor die with through-hole via on saw streets and through-hole via in active area of die'20117,872,345'Integrated circuit package system with rigid locking lead'20117,843,042'Wafer level integration package'20107,829,998'Semiconductor wafer having through-hole vias on saw streets with backside redistribution layer'20107,829,984'Integrated circuit package system stackable devices'20107,781,261'Integrated circuit package system with offset stacking and anti-flash structure'20107,776,655'Semiconductor device and method of forming conductive pillars in recessed region of peripheral area around the device for electrical interconnection to other devices'20107,741,156'Semiconductor device and method of forming through vias with reflowed conductive material'20107,709,944'Integrated circuit package system with package integration'20107,659,145'Semiconductor device and method of forming stepped-down RDL and recessed THV in peripheral region of the device'20107,585,750'Semiconductor package having through-hole via on saw streets formed with partial saw'20097,566,966'Integrated circuit package-on-package system with anti-mold flash feature'20097,553,752'Method of making a wafer level integration package'2009Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2009–2018Patents assigned to STATS CHIPPAC LTD (117)· patent assignee history
2009–2021Based in Singapore, SG· patent location history
2011–2019Patents assigned to CHUA LINDA PEI EE (78)· patent assignee history
2011–2019Patents assigned to DO BYUNG TAI (73)· patent assignee history
2011–2019Patents assigned to PAGAILA REZA A (20)· patent assignee history
2013–2017Patents assigned to ARNEL SENOSA TRASPORTO (31)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| STATS CHIPPAC LTD | 117 | 2009–2018 |
| CHUA LINDA PEI EEself | 78 | 2011–2019 |
| DO BYUNG TAI | 73 | 2011–2019 |
| ARNEL SENOSA TRASPORTO | 31 | 2013–2017 |
| PAGAILA REZA A | 20 | 2011–2019 |
Locations
| Location | Patents | Span |
|---|---|---|
| Singapore, SG | 125 | 2009–2021 |