Inventor

Mark Bluhm

Inventor

Carrollton, TX, US

Overview

36→

Patents

1988–2011

Patent span

Physics

Primary field (CPC G)

Patents· 36 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing67%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use29%

G11CStatic stores2%

H03KPulse technique2%

PatentTitleYear

7,900,075'Pipelined computer system with power management control'2011 7,900,076'Power management method for a pipelined computer system'2011 7,509,512'Instruction-initiated method for suspending operation of a pipelined data processor'2009 7,120,810'Instruction-initiated power management method for a pipelined data processor'2006 7,062,666'Signal-initiated method for suspending operation of a pipelined data processor'2006 7,000,132'Signal-initiated power management method for a pipelined data processor'2006 6,978,390'Pipelined data processor with instruction-initiated power management control'2005 6,910,141'Pipelined data processor with signal-initiated power management control'2005 6,721,894'METHOD FOR CONTROLLING POWER OF A MICROPROCESSOR BY ASSERTING AND DE-ASSERTING A CONTROL SIGNAL IN RESPONSE CONDITIONS ASSOCIATED WITH THE MICROPROCESSOR ENTERING AND EXITING LOW POWER STATE RESPECTIVELY'2004 6,694,443'SYSTEM FOR CONTROLLING POWER OF A MICROPROCESSOR BY ASSERTING AND DE-ASSERTING A CONTROL SIGNAL IN RESPONSE TO CONDITION ASSOCIATED WITH THE MICROPROCESSOR ENTERING AND EXITING LOW POWER STATE RESPECTIVELY'2004 6,343,363'Method of invoking a low power mode in a computer system using a halt instruction'2002 6,205,560'Debug system allowing programmable selection of alternate debug mechanisms such as debug handler, SMI, or JTAG'2001 6,138,230'Processor with multiple execution pipelines using pipe stage state information to control independent movement of instructions between pipe stages of an execution pipeline'2000 6,088,807'Computer system with low power mode invoked by halt instruction'2000 6,073,231'Pipelined processor with microcontrol of register translation hardware'2000 5,963,984'Address translation unit employing programmable page size'1999 5,937,178'Register file for registers with multiple addressable sizes using read-modify-write for register file update'1999 5,907,860'System and method of retiring store data from a write buffer'1999 5,898,815'I/O bus interface recovery counter dependent upon minimum bus clocks to prevent overrun and ratio of execution core clock frequency to system bus clock frequency'1999 5,860,111'Coherency for write-back cache in a system designed for write-through cache including export-on-hold'1999 5,838,897'Debugging a processor using data output during idle bus cycles'1998 5,784,589'Distributed free register tracking for register renaming using an availability tracking register associated with each stage of an execution pipeline'1998 5,771,365'Condensed microaddress generation in a complex instruction set computer'1998 5,664,149'Coherency for write-back cache in a system designed for write-through cache using an export/invalidate protocol'1997 5,644,741'Processor with single clock decode architecture employing single microROM'1997 5,632,037'Microprocessor having power management circuitry with coprocessor support'1997 5,630,143'Microprocessor with externally controllable power management'1997 5,630,149'Pipelined processor with register renaming hardware to accommodate multiple size registers'1997 5,596,731'Single clock bus transfers during burst and non-burst cycles'1997 5,584,009'System and method of retiring store data from a write buffer'1996 5,524,234'Coherency for write-back cache in a system designed for write-through cache including write-back latency control'1996 5,479,616'Exception handling for prefetched instruction bytes using valid bits to identify instructions that will cause an exception'1995 5,375,209'Microprocessor for selectively configuring pinout by activating tri-state device to disable internal clock from external pin'1994 5,159,210'Line precharging circuits and methods'1992 4,763,253'Microcomputer with change of flow'1988 4,729,093'Microcomputer which prioritizes instruction prefetch requests and data operand requests'1988

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1988Patents assigned to MOTOROLA INC (2)· patent assignee history

1988Based in Austin, TX, US· patent location history

1992–1998Patents assigned to CYRIX CORP (14)· patent assignee history

1992–2011Based in Carrollton, TX, US· patent location history

1997–2001Based in Plano, TX, US· patent location history

1999–2011Patents assigned to NAT SEMICONDUCTOR CORP (17)· patent assignee history

2000–2001Patents assigned to VIA CYRIX INC (3)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
NAT SEMICONDUCTOR CORP	17	1999–2011
CYRIX CORP	14	1992–1998
VIA CYRIX INC	3	2000–2001
MOTOROLA INC	2	1988

Locations

Location	Patents	Span
Carrollton, Texas, US	24	1992–2011
Plano, Texas, US	10	1997–2001
Austin, Texas, US	2	1988