Inventor
Naveen Kumar
Inventor
San Jose, CA, US
Overview
Patents· 90 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing34%
H03MCoding27%
G11CStatic stores15%
H04LTransmission of digital information, e.g. telegraphic communication5%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use4%
A61HPhysical therapy apparatus, e.g. devices for locating or stimulating reflex points in the body2%
G02BOptical elements, systems or apparatus2%
G06NComputing arrangements based on specific computational models2%
G06QInformation and communication technology [ict] specially adapted for administrative, commercial, financial, managerial or supervisory purposes2%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications2%
PatentTitleYear
11,051,895Robotic surgical devices, systems, and related methods202110,877,840Dynamic neighbor and bitline assisted correction for NAND flash storage202010,855,762Adopting data across different sites202010,846,172Encoding method and system for memory device including QLC cells202010,847,231Memory system with adaptive read-threshold scheme and method of operating such memory system202010,817,373Soft chip-kill recovery using concatenated codes202010,802,567Performing local power gating in a processor202010,802,835Rule-based data protection202010,728,255System and method for protection of entities across availability zones202010,714,195Read disturb detection and recovery with adaptive thresholding for 3-D NAND storage202010,707,899Bit-flipping decoder for G-LDPC codes with syndrome-decoding for component codes202010,700,706Memory system with decoders and method of operating such memory system and decoders202010,692,003Device placement optimization with reinforcement learning202010,691,540Soft chip-kill recovery for multiple wordlines failure202010,691,536Method to select flash memory blocks for refresh after read operations202010,693,496Memory system with LDPC decoder and method of operating such memory system and LDPC decoder202010,685,488Systems and methods for computer assisted operation202010,680,647Min-sum decoding for LDPC codes202010,672,497Memory system and method for bad block management202010,601,546Dynamic interleaver change for bit line failures in NAND flash storage202010,572,342Memory system with LDPC decoder and operating method thereof202010,523,245Soft decoder for generalized product codes201910,498,366Data dependency mitigation in parallel decoders for flash storage201910,492,981Systems and methods for computer assisted operation201910,491,243Deep learning for low-density parity-check (LDPC) decoding201910,489,804System and method for identifying customer persona and implementing persuasion techniques thereof201910,484,008Memory system with on-the-fly error detection and termination and operating method thereof201910,482,006System and method for automatically categorizing test cases for model based testing201910,484,020System and method for parallel decoding of codewords sharing common data201910,447,302Memory system decoding design and operating method thereof201910,439,649Data dependency mitigation in decoder architecture for generalized product codes for flash storage201910,432,363Page health prediction using product codes decoder in NAND flash storage201910,419,024Early termination of low-density parity-check (LDPC) decoding201910,412,162Adopting data across different sites201910,403,372Memory system with adaptive read-threshold scheme and method of operating such memory system201910,389,383Low-complexity LDPC encoder201910,388,400Generalized product codes for flash storage201910,365,987Synchronous hardware event collection201910,348,335Miscorrection avoidance for turbo product codes201910,335,572Systems and methods for computer assisted operation201910,326,477Techniques for miscorrection detection for constituent codewords in product codes201910,324,817Distributed hardware tracing201910,326,473Symbol-based coding for NAND flash devices201910,303,364Techniques for low-latency chase decoding of turbo product codes with soft information201910,218,388Techniques for low complexity soft decoder for turbo product codes201910,205,469Low latency soft decoder architecture for generalized product codes201910,200,066Code reconstruction scheme for multiple code rate TPC decoder201910,187,086State-based decoding of product codes201910,163,515Memory system having feature boosting and operating method thereof201810,157,097Redundant bytes utilization in error correction code201810,153,785Generalized low-density parity-check (GLDPC) code with variable length constituents201810,148,287Bit-flipping LDPC decoding algorithm with hard channel information201810,090,862Hybrid soft decoding algorithm for multiple-dimension TPC codes201810,090,865Performance optimization in soft decoding of error correcting codes201810,084,485Soft decoder parameter optimization for product codes201810,079,613Data mapping scheme for generalized product codes201810,048,965Instruction and logic for a binary translation mechanism for control-flow security201810,033,407Optimization of low density parity-check code encoder based on a search for an independent set of nodes20189,998,148Techniques for low complexity turbo product code decoding20189,954,556Scheme to avoid miscorrection for turbo product codes20189,935,659Performance optimization in soft decoding for turbo product codes20189,906,241'Apparatus and method for turbo product codes'20189,906,240'One-shot decoder for two-error-correcting BCH codes'20189,875,167Distributed hardware tracing20189,772,674'Performing local power gating in a processor'20179,741,431'Optimal read threshold estimation'20179,712,189'Error correction capability improvement in the presence of hard bit errors'20179,673,840'Turbo product codes for NAND flash'20179,606,941'Instruction and logic for a binary translation mechanism for control-flow security'20179,576,101'Configurable cell design using capacitive coupling for enhanced timing closure'20179,569,302'Decoding of turbo product codes using miscorrection detection'20179,559,727'Stopping rules for turbo product codes'20179,459,871'System of improved loop detection and execution'20169,391,641'Syndrome tables for decoding turbo-product codes'20169,337,873'Miscorrection detection for error correcting codes using bit reliabilities'20169,330,028'Instruction and logic for a binary translation mechanism for control-flow security'20169,300,329'Turbo-product codes (TPC) with interleaving'20169,251,046'Method and system for generating and processing black box test cases'20169,229,524'Performing local power gating in a processor'20169,231,623'Chase decoding for turbo-product codes (TPC) using error intersections'20169,229,870'Managing cache systems of storage systems'20169,116,729'Handling of binary translated self modifying code and cross modifying code'20158,904,263'Error correction capability improvement in the presence of hard bit errors'20148,902,530'Decision directed and non-decision directed low frequency noise cancelation in turbo detection'20148,819,642'Method and system for generating and processing black box test cases'20148,659,846'Inter-track interference cancelation in the presence of frequency offset'20148,090,834'System and method for optimizing server resources while providing interaction with documents accessible through the server'20127,673,050'System and method for optimizing server resources while providing interaction with documents accessible through the server'20107,293,255'Apparatus and method for automated creation of resource types'20076,681,242'Method and apparatus for detecting dependency cycles between resources in a computer system'2004Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2012–2020Patents assigned to KUMAR NAVEEN (9)· patent assignee history
2014–2018Patents assigned to SK HYNIX MEMORY SOLUTIONS INC (11)· patent assignee history
2014–2020Based in San Jose, CA, US· patent location history
2014–2019Based in Gaya, IN· patent location history
2015–2020Patents assigned to INTEL CORP (8)· patent assignee history
2016–2020Patents assigned to SK HYNIX INC (53)· patent assignee history
2019–2020Patents assigned to GOOGLE LLC (3)· patent assignee history
2019–2020Based in Bengaluru, IN· patent location history
2019–2020Based in Campbell, CA, US· patent location history
2020Based in Bangalore, IN· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SK HYNIX INC | 53 | 2016–2020 |
| SK HYNIX MEMORY SOLUTIONS INC | 11 | 2014–2018 |
| KUMAR NAVEENself | 9 | 2012–2020 |
| INTEL CORP | 8 | 2015–2020 |
| GOOGLE LLC | 3 | 2019–2020 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 72 | 2014–2020 |
| Bengaluru, IN | 3 | 2019–2020 |
| Gaya, IN | 3 | 2014–2019 |
| Campbell, California, US | 2 | 2019–2020 |
| Bangalore, IN | 2 | 2020 |