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Inventor

Thomas W. Dyer

Inventor
Pleasant Valley, NY, US

Overview

94→
Patents
2002–2016
Patent span
Electricity
Primary field (CPC H)

Patents· 94 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary
H10DInorganic electric semiconductor devices42%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1018%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1018%
H10BElectronic memory devices13%
H01LSemiconductor devices7%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests1%
G01RMeasuring electric variables1%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices1%
PatentTitleYear
9,455,186'Selective local metal cap layer formation for improved electromigration behavior'20169,431,535'Semiconductor devices having tensile and/or compressive stress and methods of manufacturing'20169,406,560'Selective local metal cap layer formation for improved electromigration behavior'20169,385,038'Selective local metal cap layer formation for improved electromigration behavior'20169,276,111'Semiconductor devices having tensile and/or compressive stress and methods of manufacturing'20169,171,848'Deep trench MIM capacitor and moat isolation with epitaxial semiconductor wafer scheme'20159,157,980'Measuring metal line spacing in semiconductor devices'20159,076,847'Selective local metal cap layer formation for improved electromigration behavior'20159,059,177'Doping of copper wiring structures in back end of line processing'20159,018,097'Semiconductor device processing with reduced wiring puddle formation'20158,896,069'Semiconductor devices having tensile and/or compressive stress and methods of manufacturing'20148,889,504'Semiconductor devices having tensile and/or compressive stress and methods of manufacturing'20148,853,746'CMOS devices with stressed channel regions, and methods for fabricating the same'20148,765,602'Doping of copper wiring structures in back end of line processing'20148,697,528'Method of forming a planar field effect transistor structure with recesses for epitaxially deposited source/drain regions'20148,685,806'Silicon-on-insulator substrate with built-in substrate junction'20148,623,673'Structure and method for detecting defects in BEOL processing'20148,482,009'Silicon-on-insulator substrate with built-in substrate junction'20138,377,785'Planar field effect transistor structure having an angled crystallographic etch-defined source/drain recess and a method of forming the transistor structure'20138,362,531'Method of patterning semiconductor structure and structure thereof'20138,293,631'Semiconductor devices having tensile and/or compressive stress and methods of manufacturing'20128,198,194'Methods of forming p-channel field effect transistors having SiGe source/drain regions'20128,159,031'SOI substrates and SOI devices, and methods for forming the same'20128,110,464'SOI protection for buried plate implant and DT bottle ETCH'20128,063,449'Semiconductor devices and methods of manufacture thereof'20117,989,357'Method of patterning semiconductor structure and structure thereof'20117,968,910'Complementary field effect transistors having embedded silicon source and drain regions'20117,964,910'Planar field effect transistor structure having an angled crystallographic etch-defined source/drain recess and a method of forming the transistor structure'20117,955,940'Silicon-on-insulator substrate with built-in substrate junction'20117,943,474'EDRAM including metal plates'20117,923,365'Methods of forming field effect transistors having stress-inducing sidewall insulating spacers thereon'20117,910,451'Simultaneous buried strap and buried contact via formation for SOI deep trench capacitor'20117,911,001'Methods for forming self-aligned dual stress liners for CMOS semiconductor devices'20117,906,384'Semiconductor devices having tensile and/or compressive stress and methods of manufacturing'20117,884,448'High performance 3D FET structures, and methods for forming the same using preferential crystallographic etching'20117,868,461'Embedded interconnects, and methods for forming same'20117,863,693'Forming conductive stud for semiconductive devices'20117,863,646'Dual oxide stress liner'20117,847,357'High performance CMOS devices comprising gapped dual stressors with dielectric gap fillers, and methods of fabricating the same'20107,842,592'Channel strain engineering in field-effect-transistor'20107,816,231'Device structures including backside contacts, and methods for forming same'20107,808,082'Structure and method for dual surface orientations for CMOS transistors'20107,790,542'CMOS devices having reduced threshold voltage variations and methods of manufacture thereof'20107,790,622'Methods for removing gate sidewall spacers in CMOS semiconductor fabrication processes'20107,772,095'Integrated circuit having localized embedded SiGe and method of manufacturing'20107,749,903'Gate patterning scheme with self aligned independent gate etch'20107,750,429'Self-aligned and extended inter-well isolation structure'20107,741,188'Deep trench (DT) metal-insulator-metal (MIM) capacitor'20107,736,966'CMOS devices with hybrid channel orientations and method for fabricating the same'20107,728,364'Enhanced mobility CMOS transistors with a V-shaped channel with self-alignment to shallow trench isolation'20107,718,993'Pattern enhancement by crystallographic etching'20107,667,255'Deep trench inter-well isolation structure'20107,666,721'SOI substrates and SOI devices, and methods for forming the same'20107,652,336'Semiconductor devices and methods of manufacture thereof'20107,635,899'Structure and method to form improved isolation in a semiconductor device'20097,598,540'High performance CMOS devices comprising gapped dual stressors with dielectric gap fillers, and methods of fabricating the same'20097,598,572'Silicided polysilicon spacer for enhanced contact area'20097,585,773'Non-conformal stress liner for enhanced MOSFET performance'20097,582,516'CMOS devices with hybrid channel orientations, and methods for fabricating the same using faceted epitaxy'20097,569,489'High performance 3D FET structures, and methods for forming the same using preferential crystallographic etching'20097,569,446'Semiconductor structure and method of manufacture'20097,566,949'High performance 3D FET structures, and methods for forming the same using preferential crystallographic etching'20097,560,382'Embedded interconnects, and methods for forming same'20097,550,330'Deep junction SOI MOSFET with enhanced edge body contacts'20097,528,451'CMOS gate conductor having cross-diffusion barrier'20097,518,191'Silicon on insulator devices having body-tied-to-source and methods of making'20097,517,767'Forming conductive stud for semiconductive devices'20097,504,299'Folded node trench capacitor'20097,504,309'Pre-silicide spacer removal'20097,488,659'Structure and methods for stress concentrating spacer'20097,488,660'Extended raised source/drain structure for enhanced contact area and method for forming extended raised source/drain structure'20097,485,508'Two-sided semiconductor-on-insulator structures and methods of manufacturing the same'20097,485,520'Method of manufacturing a body-contacted finfet'20097,485,516'Method of ion implantation of nitrogen into semiconductor substrate prior to oxidation for offset spacer formation'20097,482,215'Self-aligned dual segment liner and method of manufacturing the same'20097,456,450'CMOS devices with hybrid channel orientations and method for fabricating the same'20087,452,758'Process for making FinFET device with body contact and buried oxide junction isolation'20087,442,586'SOI substrate and SOI device, and method for forming the same'20087,442,614'Silicon on insulator devices having body-tied-to-source and methods of making'20087,436,030'Strained MOSFETs on separated silicon layers'20087,393,746'Post-silicide spacer removal'20087,390,745'Pattern enhancement by crystallographic etching'20087,122,437'Deep trench capacitor with buried plate electrode and isolation collar'20067,101,744'Method for forming self-aligned, dual silicon nitride liner for CMOS devices'20067,023,041'Trench capacitor vertical structure'20066,936,511'Inverted buried strap structure and method for vertical transistor DRAM'20056,897,107'Method for forming TTO nitride liner for improved collar protection and TTO reliability'20056,887,761'Vertical semiconductor devices'20056,809,368'TTO nitride liner for improved collar protection and TTO reliability'20046,794,242'Extendible process for improved top oxide layer for DRAM array and the gate interconnects while providing self-aligned gate contacts'20046,747,306'Vertical gate conductor with buried contact layer for increased contact landing area'20046,548,344'Spacer formation process using oxide shield'20036,518,616'Vertical gate top engineering for improved GC and CB process windows'20036,335,248'Dual workfunction MOSFETs with borderless diffusion contacts for high-performance embedded DRAM technology'2002

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2002–2016Patents assigned to IBM (91)· patent assignee history
2002–2016Based in Pleasant Valley, NY, US· patent location history
2003–2011Patents assigned to INFINEON TECHNOLOGIES AG (8)· patent assignee history
2005–2011Patents assigned to INFINEON TECHNOLOGIES CORP (5)· patent assignee history
2008–2012Patents assigned to SAMSUNG ELECTRONICS CO LTD (6)· patent assignee history
2011–2014Patents assigned to DYER THOMAS W (13)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
IBM912002–2016
DYER THOMAS Wself132011–2014
INFINEON TECHNOLOGIES AG82003–2011
SAMSUNG ELECTRONICS CO LTD62008–2012
INFINEON TECHNOLOGIES CORP52005–2011
Locations
LocationPatentsSpan
Pleasant Valley, New York, US942002–2016