Inventor
Barry K. Britton
Inventor
Orefield, PA, US
Overview
Patents· 39 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H03Kprimary
H03KPulse technique59%
G06FElectric digital data processing15%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses13%
H04LTransmission of digital information, e.g. telegraphic communication9%
G01RMeasuring electric variables2%
G11CStatic stores2%
PatentTitleYear
10,819,318Single event upset immune flip-flop utilizing a small-area highly resistive element20208,531,222'Phase locked loop circuit with selectable feedback paths'20138,319,521'Safe programming of key information into non-volatile memory for a programmable logic device'20128,314,634'Power control block with output glitch protection'20127,863,931'Flexible delay cell architecture'20117,696,784'Programmable logic device with multiple slice types'20107,675,321'Dual-slice architectures for programmable logic devices'20107,650,545'Programmable interconnect for reconfigurable system-on-chip'20107,605,606'Area efficient routing architectures for programmable logic devices'20097,599,457'Clock-and-data-recovery system having a multi-phase clock generator for one or more channel circuits'20097,592,834'Logic block control architectures for programmable logic devices'20097,554,357'Efficient configuration of daisy-chained programmable logic devices'20097,532,646'Distributed multiple-channel alignment scheme'20097,397,276'Logic block control architectures for programmable logic devices'20087,385,417'Dual slice architectures for programmable logic devices'20087,378,872'Programmable logic device architecture with multiple slice types'20087,262,630'Programmable termination for single-ended and differential schemes'20077,139,288'Protocol-independent packet delineation for backplane architecture'20067,034,596'Adaptive input logic for phase adjustments'20066,940,779'Programmable broadcast initialization of memory blocks'20056,873,187'Method and apparatus for controlling signal distribution in an electronic circuit'20056,483,342'Multi-master multi-slave system bus in a field programmable gate array (FPGA)'20026,472,904'Double data rate input and output in a programmable logic device'20026,216,191'Field programmable gate array having a dedicated processor interface'20016,064,225'Global signal distribution with reduced routing tracks in an FPGA'20006,060,902'Programmable clock manager for a programmable logic device that can be programmed without reconfiguring the device'20006,049,224'Programmable logic device with logic cells having a flexible input structure'20006,043,677'Programmable clock manager for a programmable logic device that can implement delay-locked loop functions'20006,028,463'Programmable clock manager for a programmable logic device that can generate at least two different output clocks'20006,020,755'Hybrid programmable gate arrays'20005,986,471'Bi-directional buffers and supplemental logic and interconnect cells for programmable logic devices'19995,623,217'Field programmable gate array with write-port enabled memory'19975,528,170'Low-skew signal routing in a programmable array'19965,396,126'FPGA with distributed switch matrix'19955,394,031'Apparatus and method to improve programming speed of field programmable gate arrays'19955,386,156'Programmable function unit with programmable fast ripple logic'19955,384,497'Low-skew signal routing in a programmable array'19955,381,058'FPGA having PFU with programmable output driver inputs'19955,311,080'Field programmable gate array with direct input/output connection'1994Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1994–1997Based in Schnecksville, PA, US· patent location history
1995–1996Patents assigned to AT & T CORP (6)· patent assignee history
1997–2001Patents assigned to LUCENT TECHNOLOGIES INC (8)· patent assignee history
1999–2010Based in Orefield, PA, US· patent location history
2002–2013Patents assigned to LATTICE SEMICONDUCTOR CORP (20)· patent assignee history
2006–2010Patents assigned to AGERE SYSTEMS INC (2)· patent assignee history
2009–2011Based in Allentown, PA, US· patent location history
2012–2013Patents assigned to BRITTON BARRY (3)· patent assignee history
2012–2020Based in Slatington, PA, US· patent location history
2012Based in Hillsboro, OR, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| LATTICE SEMICONDUCTOR CORP | 20 | 2002–2013 |
| LUCENT TECHNOLOGIES INC | 8 | 1997–2001 |
| AT & T CORP | 6 | 1995–1996 |
| BRITTON BARRYself | 3 | 2012–2013 |
| AGERE SYSTEMS INC | 2 | 2006–2010 |
Locations
| Location | Patents | Span |
|---|---|---|
| Orefield, Pennsylvania, US | 25 | 1999–2010 |
| Schnecksville, Pennsylvania, US | 8 | 1994–1997 |
| Slatington, Pennsylvania, US | 3 | 2012–2020 |
| Allentown, Pennsylvania, US | 2 | 2009–2011 |
| Hillsboro, OR, US | 1 | 2012 |