Inventor
Wei Ti Lee
Inventor
San Jose, CA, US
Overview
Patents· 26 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
C23Cprimary
C23CCoating metallic material15%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1015%
H01LSemiconductor devices10%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1010%
G01NInvestigating or analysing materials by determining their chemical or physical properties9%
H10NElectric solid-state devices not otherwise provided for9%
G01BMeasuring length, thickness or similar linear dimensions7%
H10BElectronic memory devices6%
H10DInorganic electric semiconductor devices6%
Y10TTechnical subjects covered by former us classification6%
PatentTitleYear
10,801,978XPS metrology for process control in selective deposition202010,648,802Feed-forward of multi-layer and multi-process information using XPS and XRF technologies202010,533,961Method and system for non-destructive metrology of thin layers202010,082,390Feed-forward of multi-layer and multi-process information using XPS and XRF technologies20189,952,166Silicon germanium thickness and composition determination using combined XPS and XRF technologies20189,926,639'Methods for forming barrier/seed layers for copper interconnect structures'20189,818,939'Resistive switching devices having a switching layer and an intermediate electrode layer and methods of formation thereof'20179,594,035'Silicon germanium thickness and composition determination using combined XPS and XRF technologies'20179,593,417'Gas line weldment design and process for CVD aluminum'20179,252,359'Resistive switching devices having a switching layer and an intermediate electrode layer and methods of formation thereof'20169,129,945'Formation of liner and barrier for tungsten as gate electrode and as contact plug to reduce resistance and enhance device performance'20159,099,633'Solid electrolyte memory elements with electrode interface for improved performance'20158,895,953'Programmable memory elements, devices and methods having physically localized structure'20148,866,122'Resistive switching devices having a buffer layer and methods of formation thereof'20148,847,192'Resistive switching devices having alloyed electrodes and methods of formation thereof'20148,637,390'Metal gate structures and methods for forming thereof'20148,535,443'Gas line weldment design and process for CVD aluminum'20137,867,900'Aluminum contact integration on cobalt silicide junction'20117,857,947'Unique passivation technique for a CVD blocker plate to prevent particle formation'20107,824,743'Deposition processes for titanium nitride barrier and aluminum'20107,699,295'Ampoule splash guard apparatus'20107,464,917'Ampoule splash guard apparatus'20087,378,002'Aluminum sputtering while biasing wafer'20086,716,733'CVD-PVD deposition process'20046,656,831'Plasma-enhanced chemical vapor deposition of a metal nitride layer'20036,528,180'Liner materials'2003Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2003–2018Patents assigned to APPLIED MATERIALS INC (13)· patent assignee history
2003–2020Based in San Jose, CA, US· patent location history
2013–2018Patents assigned to LEE WEI TI (9)· patent assignee history
2014–2017Patents assigned to ADESTO TECHNOLOGIES CORP (6)· patent assignee history
2014–2018Patents assigned to GANGULI SESHADRI (3)· patent assignee history
2018–2020Patents assigned to NOVA MEASURING INSTR INC (5)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| APPLIED MATERIALS INC | 13 | 2003–2018 |
| LEE WEI TIself | 9 | 2013–2018 |
| ADESTO TECHNOLOGIES CORP | 6 | 2014–2017 |
| NOVA MEASURING INSTR INC | 5 | 2018–2020 |
| GANGULI SESHADRI | 3 | 2014–2018 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 26 | 2003–2020 |