Inventor
TZE-LIANG LEE
Inventor
TW
Overview
Patents· 118 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices27%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1021%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1019%
H10DInorganic electric semiconductor devices17%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices5%
C23CCoating metallic material4%
B82YSpecific uses or applications of nanostructures2%
C04BLime, magnesia1%
C07FAcyclic, carbocyclic or heterocyclic compounds containing elements other than carbon, hydrogen, halogen, oxygen, nitrogen, sulfur, selenium or tellurium1%
G01VGeophysics1%
PatentTitleYear
12,598,767Dielectric layers for semiconductor devices and methods of forming the same202612,564,028Dielectric layers having nitrogen-containing crusted surfaces202612,557,572Method for manufacturing a semiconductor device202612,557,620Transistor contacts and methods of forming the same202612,512,408Semiconductor devices including backside power via and methods of forming the same202512,494,368Photoresist and method202512,487,523In-situ deposition and densification treatment for metal-comprising resist layer202512,463,034Photoresist layer surface treatment, cap layer, and method of forming photoresist pattern202512,453,144Semiconductor device comprising first etch stop layer over first conductive feature over source/drain region202512,438,041Interconnect structure and method of forming the same202512,417,948Hybrid film scheme for self-aligned contact202512,408,367Semiconductor device202512,387,974Patterning interconnects and other structures by photo-sensitizing method202512,374,616Semiconductor device and method for manufacturing the same202512,374,548Photoresist layer outgassing prevention202512,368,098Methods of forming semiconductor device202512,347,726Interconnect structures and methods of forming the same202512,341,011Method for forming and using mask202512,322,590Semiconductor device and method202512,324,185Semiconductor device, FinFET device and methods of forming the same202512,322,647Semiconductor devices and methods202512,315,726Semiconductor device and method202512,308,283Method for forming interconnect structure202512,308,309Semiconductor device with integrated metal-insulator-metal capacitors202512,310,070Semiconductor device and method of manufacturing the same202512,302,595Dummy hybrid film for self-alignment contact formation202512,293,916Surface oxidation control of metal gates using capping layer202512,283,617Interconnect features with sharp corners and method forming same202512,271,113Method of manufacturing a semiconductor device202512,272,554Method of manufacturing a semiconductor device202512,261,036Forming low-stress silicon nitride layer through hydrogen treatment202512,255,095Semiconductor structure and manufacturing method thereof202512,255,240Topology selective and sacrificial silicon nitride layer for generating spacers for a semiconductor device drain202512,255,138Interconnect structures of semiconductor device and methods of forming the same202512,237,224Semiconductor device and method202512,237,419Gate structures in transistor devices and methods of forming same202512,230,567Semiconductor structure and manufacturing method thereof202512,222,643Method of manufacturing a semiconductor device and pattern formation method202512,217,971Method for forming semiconductor device202512,211,924Semiconductor device and method of forming the same202512,211,766Highly protective wafer edge sidewall protection layer202512,205,824Patterning material including silicon-containing layer and method for semiconductor device fabrication202512,198,979Semiconductor device with multi-layer etch stop structure202512,183,577Metal hard masks for reducing line bending202412,159,787Method of manufacturing a semiconductor device and pattern formation method202412,153,346Photoresist for semiconductor fabrication202412,154,973Fin field-effect transistor device and method202412,142,651Integrated circuit multi-gate transistors structure with gate via and manufacturing method thereof202412,142,608Semiconductor device and method for making the same202412,135,501Method of manufacturing a semiconductor device202412,125,911Method of modulating stress of dielectric layers202412,110,587Deposition apparatus and method with EM radiation202412,107,163Semiconductor device structure having dislocation stress memorization and methods of forming the same202412,094,930Integrated circuit structure and method for forming the same202412,087,644Methods of determining process recipes and forming a semiconductor device202412,087,838Self-aligned contact hard mask structure of semiconductor device and method of forming same202412,074,058Patterning methods for semiconductor devices202412,057,315Photoresist layer surface treatment, cap layer, and method of forming photoresist pattern202412,051,735Dielectric spacer to prevent contacting shorting202412,046,475Surface oxidation control of metal gates using capping layer202412,044,966Photoresist for semiconductor fabrication202412,033,890Patterning interconnects and other structures by photo-sensitizing method202412,027,423Forming isolation regions for separating fins and gate stacks202412,014,922Apparatus for manufacturing a thin film and a method therefor202412,002,675Photoresist layer outgassing prevention202412,002,865Interconnect features with sharp corners and method forming same202411,984,485Semiconductor device, FinFET device and methods of forming the same202411,978,641Wafer bonding method and semiconductor structure obtained by the same202411,973,027Semiconductor device and methods of forming the same202411,948,798Semiconductor device and method202411,929,281Reducing oxidation by etching sacrificial and protection layer separately202411,929,329Damascene process using cap layer202411,923,294Interconnect structures of semiconductor device and methods of forming the same202411,901,409Semiconductor device and method of manufacturing the same202411,894,435Contact plug structure of semiconductor device and method of forming same202411,887,851Method for forming and using mask202411,854,798Semiconductor device and method202311,848,231Method for forming semiconductor device with multi-layer etch stop structure202311,842,922Method for forming interconnect structure202311,830,727Forming low-stress silicon nitride layer through hydrogen treatment202311,824,120Method of fabricating a source/drain recess in a semiconductor device202311,822,237Method of manufacturing a semiconductor device202311,798,984Seamless gap fill202311,784,046Method of manufacturing a semiconductor device202311,773,506Wafer susceptor with improved thermal characteristics202311,749,752Doping profile for strained source/drain region202311,749,756Method for manufacturing semiconductor device202311,742,399Topology selective and sacrificial silicon nitride layer for generating spacers for a semiconductor device drain202311,726,405Photoresist for semiconductor fabrication202311,725,278Systems and methods for a plasma enhanced deposition of material on a semiconductor substrate202311,715,640Patterning material including silicon-containing layer and method for semiconductor device fabrication202311,705,332Photoresist layer surface treatment, cap layer, and method of forming photoresist pattern202311,676,852Patterning methods for semiconductor devices202311,676,855Patterning interconnects and other structures by photo-sensitizing method202311,670,546Semiconductor structure and manufacturing method thereof202311,670,500Treatment system and method202311,652,106Semiconductor device and method for making the same202311,588,030Integrated circuit structure and manufacturing method thereof202311,502,196Stress modulation for dielectric layers202211,482,411Semiconductor device and method202211,441,221Method of performing atomic layer deposition202211,437,515Source and drain stressors with recessed top surfaces202211,437,277Forming isolation regions for separating fins and gate stacks202211,411,109MOS devices having epitaxy regions with reduced facets202211,395,373Wafer holder with tapered region202211,393,674Forming low-stress silicon nitride layer through hydrogen treatment202211,373,947Methods of forming interconnect structures of semiconductor device202211,342,444Dielectric spacer to prevent contacting shorting202211,328,952Interconnect structure and method202211,289,417Semiconductor device and methods of forming the same202211,282,712Method for preventing bottom layer wrinkling in a semiconductor device202211,282,742Semiconductor device with multi-layer etch stop structure and method for forming the same202211,271,083Semiconductor device, FinFET device and methods of forming the same202211,257,951Method of making semiconductor device having first and second epitaxial materials202211,244,822Apparatus for manufacturing a thin film and a method therefor202211,239,310Seamless gap fill202211,164,789Method for forming semiconductor device that includes covering metal gate with multilayer dielectric202111,164,948Field-effect transistor and method of manufacturing the same2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2026Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (118)· patent assignee history
2021–2026Based in TW· patent location history
2025Patents assigned to TAIWAN SEMICODUCTOR MFG COMPANY LTD (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG CO LTD | 118 | 2021–2026 |
| TAIWAN SEMICODUCTOR MFG COMPANY LTD | 1 | 2025 |
Locations
| Location | Patents | Span |
|---|---|---|
| TW | 118 | 2021–2026 |