Inventor
Andreas D. Stricker
Inventor
Essex Junction, VT, US
Overview
Patents· 39 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices39%
H01LSemiconductor devices11%
G06FElectric digital data processing8%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h106%
G01RMeasuring electric variables5%
G02BOptical elements, systems or apparatus5%
G11BInformation storage based on relative movement between record carrier and transducer4%
H02HEmergency protective circuit arrangements4%
H03KPulse technique4%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h104%
PatentTitleYear
11,105,980Demultiplexer and related method to process multiplexed optical inputs202110,985,156Electrostatic discharge clamp with reduced off-state power consumption202110,770,892Space efficient and power spike resistant ESD power clamp with digitally timed latch202010,770,412Guard ring for photonic integrated circuit die202010,444,433Waveguides including a patterned dielectric layer201910,170,460Voltage balanced stacked clamp201910,003,191Space efficient and power spike resistant ESD power clamp with digitally timed latch20189,978,743Voltage balanced stacked clamp20189,940,986Electrostatic discharge protection structures for eFuses20189,660,114'Temperature stabilization of an on-chip temperature-sensitive element'20179,601,139'Electrostatic discharge protection for a magnetoresistive sensor'20179,568,538'Matching of bipolar transistor pair through electrical stress'20179,318,217'Programming an electrical fuse with a silicon-controlled rectifier'20169,279,862'Electrostatic discharge protection for a magnetoresistive sensor'20168,946,799'Silicon controlled rectifier with stress-enhanced adjustable trigger voltage'20158,908,334'Electrostatic discharge protection for a magnetoresistive sensor'20148,586,423'Silicon controlled rectifier with stress-enhanced adjustable trigger voltage'20138,405,186'Transistor structure with a sidewall-defined intrinsic base to extrinsic base link-up region and method of forming the structure'20138,242,584'Structure and method to create stress trench'20127,932,541'High performance collector-up bipolar transistor'20117,888,745'Bipolar transistor with dual shallow trench isolation and low base resistance'20117,791,105'Device structures for a high voltage junction field effect transistor manufactured using a hybrid orientation technology wafer and design structures for a high voltage integrated circuit'20107,709,930'Tuneable semiconductor device with discontinuous portions in the sub-collector'20107,696,034'Methods of base formation in a BiCOMS process'20107,442,595'Bipolar transistor with collector having an epitaxial Si:C region'20087,390,721'Methods of base formation in a BiCMOS process'20087,288,827'Self-aligned mask formed utilizing differential oxidation rates of materials'20077,253,096'Bipolar transistor having raised extrinsic base with selectable self-alignment and methods of forming same'20077,180,157'Bipolar transistor with a very narrow emitter feature'20077,170,083'Bipolar transistor with collector having an epitaxial Si:C region'20077,136,268'Tunable ESD trigger and power clamp circuit'20067,005,686'Mixed voltage tolerant electrostatic discharge protection silicon controlled rectifier with enhanced turn-on time'20067,002,221'Bipolar transistor having raised extrinsic base with selectable self-alignment and methods of forming same'20066,965,133'Method of base formation in a BiCMOS process'20056,906,401'Method to fabricate high-performance NPN transistors in a BiCMOS process'20056,864,560'Bipolar transistor structure with a shallow isolation extension region providing reduced parasitic capacitance'20056,858,485'Method for creation of a very narrow emitter feature'20056,844,225'Self-aligned mask formed utilizing differential oxidation rates of materials'20056,809,024'Method to fabricate high-performance NPN transistors in a BiCMOS process'2004Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2004–2020Patents assigned to IBM (33)· patent assignee history
2004–2021Based in Essex Junction, VT, US· patent location history
2012–2013Patents assigned to GAUTHIER JR ROBERT J (2)· patent assignee history
2012–2013Patents assigned to PHELPS RICHARD A (2)· patent assignee history
2013Patents assigned to CAMILLO-CASTILLO RENATA (2)· patent assignee history
2013–2020Based in Milpitas, CA, US· patent location history
2016–2020Patents assigned to GLOBALFOUNDRIES INC (4)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 33 | 2004–2020 |
| GLOBALFOUNDRIES INC | 4 | 2016–2020 |
| CAMILLO-CASTILLO RENATA | 2 | 2013 |
| GAUTHIER JR ROBERT J | 2 | 2012–2013 |
| PHELPS RICHARD A | 2 | 2012–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Essex Junction, VT, US | 32 | 2004–2021 |
| Milpitas, California, US | 7 | 2013–2020 |