Inventor
Kunal Shrotri
Inventor
Boise, ID, US
Overview
Patents· 30 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices28%
H10BElectronic memory devices28%
H10DInorganic electric semiconductor devices17%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1017%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h106%
C23CCoating metallic material2%
G11CStatic stores2%
H05KPrinted circuits2%
PatentTitleYear
11,094,705Methods of forming an array of elevationally-extending strings of memory cells, methods of forming polysilicon, elevationally-extending strings of memory cells individually comprising a programmable charge storage transistor, and electronic components comprising polysilicon202111,088,017Stair step structures including insulative materials, and related devices202111,037,797Arrays of elevationally-extending strings of memory cells and methods used in forming an array of elevationally-extending strings of memory cells202111,011,538Transistors and arrays of elevationally-extending strings of memory cells202110,971,360Methods of forming a channel region of a transistor and methods used in forming a memory array202110,749,041Programmable charge storage transistor, an array of elevationally-extending strings of memory cells, methods of forming Si3Nx, methods of forming insulator material that is between a control gate and charge-storage material of a programmable charge-storage transistor, methods of forming an array of elevationally-extending strings of memory cells, a programmable charge-storage transistor manufactured in accordance with methods, and an array of elevationally-extending strings of memory cells man202010,720,446Integrated structures including material containing silicon, nitrogen, and at least one of carbon, oxygen, boron and phosphorus202010,665,469Arrays of elevationally-extending strings of memory cells and methods used in forming an array of elevationally-extending strings of memory cells202010,615,174Elevationally-extending strings of memory cells individually comprising a programmable charge storage transistor and methods of processing silicon nitride-comprising materials202010,600,682Semiconductor devices including a stair step structure, and related methods202010,586,807Arrays of elevationally-extending strings of memory cells having a stack comprising vertically-alternating insulative tiers and wordline tiers and horizontally-elongated trenches in the stacks202010,580,792Integrated structures and methods of forming integrated structures202010,559,466Methods of forming a channel region of a transistor and methods used in forming a memory array202010,483,407Methods of forming si201910,388,665Methods of forming an array of elevationally-extending strings of memory cells having a stack comprising vertically-alternating insulative tiers and wordline tiers and horizontally-elongated trenches in the stack201910,381,377Elevationally-extending strings of memory cells individually comprising a programmable charge storage transistor and methods of processing silicon nitride-comprising materials201910,381,367Methods of forming an array of elevationally-extending strings of memory cells, methods of forming polysilicon, elevationally-extending strings of memory cells individually comprising a programmable charge storage transistor, and electronic components comprising polysilicon201910,304,749Method and apparatus for improved etch stop layer or hard mask layer of a memory device201910,297,611Transistors and arrays of elevationally-extending strings of memory cells201910,269,625Methods of forming semiconductor structures having stair step structures201910,217,755Flash memory cells, components, and methods201910,157,933Integrated structures including material containing silicon, nitrogen, and at least one of carbon, oxygen, boron and phosphorus201810,121,799Elevationally-extending strings of memory cells individually comprising a programmable charge storage transistor and methods of processing silicon nitride-comprising materials201810,096,610Polysilicon doping controlled 3D NAND etching201810,083,984Integrated structures and methods of forming integrated structures201810,014,311Methods of forming an array of elevationally-extending strings of memory cells, methods of forming polysilicon, elevationally-extending strings of memory cells individually comprising a programmable charge storage transistor, and electronic components comprising polysilicon20189,893,083'Elevationally-extending strings of memory cells individually comprising a programmable charge storage transistor and methods of processing silicon nitride-comprising materials'20189,773,805'Integrated structures and methods of forming integrated structures'20179,153,455'Methods of forming semiconductor device structures, memory cells, and arrays'20159,064,692'DRAM cells and methods of forming silicon dioxide'2015Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2015–2021Patents assigned to MICRON TECHNOLOGY INC (27)· patent assignee history
2015Patents assigned to AHMED FAWAD (1)· patent assignee history
2015Patents assigned to SHROTRI KUNAL (1)· patent assignee history
2015Patents assigned to SRIVASTAVA SHIVANI (1)· patent assignee history
2015–2021Based in Boise, ID, US· patent location history
2018–2019Patents assigned to INTEL CORP (3)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MICRON TECHNOLOGY INC | 27 | 2015–2021 |
| INTEL CORP | 3 | 2018–2019 |
| AHMED FAWAD | 1 | 2015 |
| SHROTRI KUNALself | 1 | 2015 |
| SRIVASTAVA SHIVANI | 1 | 2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Boise, ID, US | 30 | 2015–2021 |