Inventor
Paul B. Ricci
Inventor
Laguna Niguel, CA, US
Overview
Patents· 21 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing65%
G11BInformation storage based on relative movement between record carrier and transducer30%
H03MCoding4%
PatentTitleYear
9,001,443'Method and system for testing a controller of a hard disk drive'20158,638,512'Accumulator for non-return to zero (NRZ) linear feedback shift register (LFSR) in controller for disk drive'20148,270,107'Accumulator for non-return to zero (NRZ) linear feedback shift register (LFSR) in controller for disk drive'20128,031,422'Accumulator for non-return to zero (NRZ) linear feedback shift register (LFSR) in controller for disk drive'20117,836,379'Method for computing buffer ECC'20107,813,067'Accumulator for non-return to zero (NRZ) linear feedback shift register (LFSR) in controller for disk drive'20107,559,009'System and method for performing parity checks in disk storage systems'20097,543,214'Method and system for performing CRC'20097,111,228'System and method for performing parity checks in disk storage system'20067,080,188'Method and system for embedded disk controllers'20065,809,533'Dual bus system with multiple processors having data coherency maintenance'19985,553,259'Apparatus and method for synchronizing the simultaneous loading of cache program word addresses in dual slice registers'19965,553,263'Cache memory system with fault tolerance having concurrently operational cache controllers processing disjoint groups of memory'19965,511,224'Configurable network using dual system busses with common protocol compatible for store-through and non-store-through cache memories'19965,509,127'Transmission logic apparatus for dual bus network'19965,495,585'Programmable timing logic system for dual bus interface'19965,444,860'Translator system for message transfers between digital units operating on different message protocols and different clock rates'19955,442,754'Receiving control logic system for dual bus network'19955,404,462'Dual bus interface transfer system for central processing module'19955,293,496'Inhibit write apparatus and method for preventing bus lockout'19945,293,621'Varying wait interval retry apparatus and method for preventing bus lockout'1994Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1994–1998Patents assigned to UNISYS CORP (11)· patent assignee history
1994–1998Based in Laguna Niguel, CA, US· patent location history
2006–2015Patents assigned to MARVELL INT LTD (10)· patent assignee history
2006–2015Based in Coto de Caza, CA, US· patent location history
2010Based in Rancho Santa Margarita, CA, US· patent location history
2012–2014Patents assigned to HUDIONO LIM (2)· patent assignee history
2012Patents assigned to RICCI PAUL B (1)· patent assignee history
2014Patents assigned to RICCI PAUL (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| UNISYS CORP | 11 | 1994–1998 |
| MARVELL INT LTD | 10 | 2006–2015 |
| HUDIONO LIM | 2 | 2012–2014 |
| RICCI PAULself | 1 | 2014 |
| RICCI PAUL Bself | 1 | 2012 |
Locations
| Location | Patents | Span |
|---|---|---|
| Laguna Niguel, California, US | 11 | 1994–1998 |
| Coto de Caza, California, US | 9 | 2006–2015 |
| Rancho Santa Margarita, California, US | 1 | 2010 |