Inventor

Natividad Vasquez, Jr.

Inventor
San Francisco, CA, US

Overview

20→
Patents
2014–2020
Patent span
Electricity
Primary field (CPC H)

Patents· 20 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Nprimary
H10NElectric solid-state devices not otherwise provided for32%
H01LSemiconductor devices28%
H10BElectronic memory devices22%
H10DInorganic electric semiconductor devices8%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h105%
A61FFilters implantable into blood vessels2%
A61MDevices for introducing media into, or onto, the body2%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h102%
PatentTitleYear
10,873,023Using aluminum as etch stop layer202010,749,110Memory stack liner comprising dielectric block layer material202010,522,754Liner layer for dielectric block layer201910,319,908Integrative resistive memory in backend metal layers201910,290,801Scalable silicon based resistive memory device201910,192,927Semiconductor device for a non-volatile (NV) resistive memory and array structure for an array of NV resistive memory201910,115,819Recessed high voltage metal oxide semiconductor transistor for RRAM cell201810,096,653Monolithically integrated resistive memory using integrated-circuit foundry compatible processes201810,062,845Flatness of memory cell surfaces20189,741,765'Monolithically integrated resistive memory using integrated-circuit foundry compatible processes'20179,601,690'Sub-oxide interface layer for two-terminal memory'20179,595,670'Resistive random access memory (RRAM) cell and method for forming the RRAM cell'20179,583,701'Methods for fabricating resistive memory device switching material using ion implantation'20179,437,814'Mitigating damage from a chemical mechanical planarization process'20169,425,046'Method for surface roughness reduction after silicon germanium thin film deposition'20169,412,790'Scalable RRAM device architecture for a non-volatile memory device and method'20169,339,630'Retractable drug delivery system and method'20169,166,163'Sub-oxide interface layer for two-terminal memory'20158,946,667'Barrier structure for a silver based RRAM and method'20158,716,098'Selective removal method and structure of silver in resistive switching device for a non-volatile memory device'2014

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2014–2020Patents assigned to CROSSBAR INC (19)· patent assignee history
2014–2016Patents assigned to VASQUEZ NATIVIDAD (3)· patent assignee history
2014–2020Based in San Francisco, CA, US· patent location history
2015Patents assigned to CLARK MARK HAROLD (1)· patent assignee history
2015Patents assigned to GEE HARRY (1)· patent assignee history
2016Patents assigned to COOK BRIAN (1)· patent assignee history
2016Based in Windsor, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
CROSSBAR INC192014–2020
VASQUEZ NATIVIDADself32014–2016
CLARK MARK HAROLD12015
COOK BRIAN12016
GEE HARRY12015
Locations
LocationPatentsSpan
San Francisco, California, US192014–2020
Windsor, California, US12016