Inventor
Sug-hun Hong
Inventor
Yongin-si, KR
Overview
Patents· 22 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices36%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1031%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1021%
H01LSemiconductor devices10%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%
PatentTitleYear
9,543,300'CMOS transistor, semiconductor device including the transistor, and semiconductor module including the device'20179,287,199'CMOS transistor, semiconductor device including the transistor, and semiconductor module including the device'20169,236,313'Method of fabricating semiconductor device having dual gate'20168,932,922'Method of fabricating semiconductor device having dual gate'20158,513,740'Complementary metal oxide semiconductor device having metal gate stack structure and method of manufacturing the same'20138,367,502'Method of manufacturing dual gate semiconductor device'20138,293,599'Methods of forming semiconductor devices having gates with different work functions using selective injection of diffusion inhibiting materials'20127,972,950'Method of fabricating semiconductor device having dual gate'20117,910,421'Methods of forming devices including different gate insulating layers on PMOS/NMOS regions'20117,696,563'Non-volatile memory device and method of manufacturing the same'20107,692,196'Memory devices and methods of manufacturing the same'20107,319,062'Trench isolation method with an epitaxially grown capping layer'20087,053,006'Methods of fabricating oxide layers by plasma nitridation and oxidation'20066,930,062'Methods of forming an oxide layer in a transistor having a recessed gate'20056,642,596'Semiconductor device having trench isolation structure and method of forming same'20036,624,496'Method of forming T-shaped isolation layer, method of forming elevated salicide source/drain region using the same, and semiconductor device having T-shaped isolation layer'20036,501,149'Semiconductor device having trench isolation structure and method of forming same'20026,383,877'Method of forming T-shaped isolation layer, method of forming elevated salicide source/drain region using the same, and semiconductor device having T-shaped isolation layer'20026,255,194'Trench isolation method'20016,037,237'Trench isolation methods utilizing composite oxide films'20005,926,721'Isolation method for semiconductor device using selective epitaxial growth'19995,903,040'Trench isolated integrated circuits including voids'1999Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1999–2017Patents assigned to SAMSUNG ELECTRONICS CO LTD (21)· patent assignee history
1999–2008Based in Seoul, KR· patent location history
2002–2003Based in Suwon-si, KR· patent location history
2002–2006Based in Kyungki-do, KR· patent location history
2005–2012Based in Gyeonggi-do, KR· patent location history
2010–2017Based in Yongin-si, KR· patent location history
2012–2016Patents assigned to HONG HYUNG-SEOK (5)· patent assignee history
2012–2016Patents assigned to HONG SUG-HUN (5)· patent assignee history
2012–2016Patents assigned to HYUN SANG-JIN (5)· patent assignee history
2012–2016Patents assigned to PARK HONG-BAE (5)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SAMSUNG ELECTRONICS CO LTD | 21 | 1999–2017 |
| HONG HYUNG-SEOK | 5 | 2012–2016 |
| HONG SUG-HUNself | 5 | 2012–2016 |
| HYUN SANG-JIN | 5 | 2012–2016 |
| PARK HONG-BAE | 5 | 2012–2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| Yongin-si, KR | 9 | 2010–2017 |
| Seoul, KR | 5 | 1999–2008 |
| Gyeonggi-do, KR | 3 | 2005–2012 |
| Suwon-si, KR | 3 | 2002–2003 |
| Kyungki-do, KR | 2 | 2002–2006 |