Inventor
James E. Miller
Inventor
Boise, ID, US
Overview
Patents· 91 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores15%
Y02EReduction of greenhouse gas [ghg] emissions, related to energy generation, transmission or distribution8%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses6%
G01RMeasuring electric variables6%
H03KPulse technique5%
H01MProcesses or means, e.g. batteries, for the direct conversion of chemical energy into electrical energy4%
C01BNon-metallic elements4%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests4%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h103%
G06FElectric digital data processing3%
PatentTitleYear
10,970,747Access and control for driving of autonomous vehicle202110,800,665Redox-active oxide materials for thermal energy storage202010,801,756Methods for operating solar-thermochemical processes202010,214,700Methods utilizing durable functional materials for chemical processes that include an oxidation step201910,186,711Photocatalytic methods for preparation of electrocatalyst materials201910,107,268Thermal energy storage and power generation systems and methods201810,106,727Proppant compositions and methods of use201810,001,298Methods for operating solar-thermochemical processes20189,868,636'Thermochemically active iron titanium oxide materials'20189,580,326'Method for carbon dioxide splitting'20179,556,528'Hybrid metal oxide cycle water splitting'2017PP027249'Satsuma hybrid named ‘Sonet’'20169,406,828'Compact photovoltaic generation assembly and power supply'20169,279,188'Hybrid metal oxide cycle water splitting'20168,637,760'Compact photovoltaic generation assembly and power supply'20148,609,573'Photocatalytic methods for preparation of electrocatalyst materials'20138,540,796'Sintering and ripening resistant noble metal nanostructures'20138,541,146'Photocatalytic methods for preparation of electrocatalyst materials'20138,281,193'Method of protecting a test circuit'20128,086,920'Method of controlling a test mode of a circuit'20117,615,240'Method and composition for the control of gastrointestinal parasites in animals'20097,582,826'Compact photovoltaic generation assembly and power supply'20097,527,671'Regenerable particulate filter'20097,400,544'Actively driven VREF for input buffer noise immunity'20087,376,874'Method of controlling a test mode of a circuit'20087,338,590'Water-splitting using photocatalytic porphyrin-nanotube composite devices'20086,917,230'Low pass filters in DLL circuits'20056,898,144'Actively driven VREF for input buffer noise immunity'20056,882,587'Method of preparing to test a capacitor'20056,791,381'Method and apparatus for reducing the lock time of a DLL'20046,778,452'Circuit and method for voltage regulation in a semiconductor device'20046,760,875'Method of testing a circuit using an output vector'20046,664,830'Low pass filters in DLL circuits'20036,600,687'Method of compensating for a defect within a semiconductor device'20036,597,619'Actively driven VREF for input buffer noise immunity'20036,591,386'Method to prevent inadvertent test mode entry'20036,469,944'Method of compensating for a defect within a semiconductor device'20026,452,846'Driver circuit for a voltage-pulling device'20026,445,629'Method of stressing a memory device'20026,441,668'Digital device with internal differential signal generator'20026,421,800'Circuit and method to prevent inadvertent test mode entry'20026,418,071'Method of testing a memory cell'20026,392,458'Method and apparatus for digital delay locked loop circuits'20026,388,480'Method and apparatus for reducing the lock time of DLL'20026,359,482'Method and apparatus for digital delay locked loop circuits'20026,353,564'Method of testing a memory array'20026,335,888'Margin-range apparatus for a sense amp\'s voltage-pulling transistor'20026,316,976'Method and apparatus for improving the performance of digital delay locked loop circuits'20016,300,668'High resistance integrated circuit resistor'20016,289,479'Circuit to prevent inadvertent test mode entry'20016,281,726'Device and method in a delay locked loop for generating quadrature and other off-phase clocks with improved resolution'20016,232,148'Method and apparatus leads-between-chips'20016,226,210'Method of detecting a short from a digit line pair to ground'20016,198,676'Test device'20016,188,622'Method of identifying a defect within a memory circuit'20016,181,617'Method and apparatus for testing a semiconductor device'20016,138,258'Circuit and method to prevent inadvertent test mode entry'20006,137,334'Logic circuit delay stage and delay line utilizing same'20006,137,325'Device and methods in a delay locked loop for generating quadrature and other off-phase clocks with improved resolution'20006,069,506'Method and apparatus for improving the performance of digital delay locked loop circuits'20006,061,430'Enhanced telephony system for premises monitoring'20006,052,322'Memory circuit voltage regulator'20006,028,799'Memory circuit voltage regulator'20006,026,040'Method of altering the margin affecting a memory cell'20006,011,731'Cell plate regulator'20005,990,538'High resistivity integrated circuit resistor'19995,982,687'Method of detecting leakage within a memory cell capacitor'19995,944,845'Circuit and method to prevent inadvertent test mode entry'19995,936,974'Circuit and method for testing an integrated circuit'19995,934,537'Device for pushing or pulling using gripping'19995,894,165'Leads between chips assembly'19995,877,993'Memory circuit voltage regulator'19995,808,897'Integrated circuit device having interchangeable terminal connection'19985,787,096'Circuit and method for testing an integrated circuit'19985,770,480'Method of leads between chips assembly'19985,751,260'Sensory integrated data interface'19985,734,661'Method and apparatus for providing external access to internal integrated circuit test circuits'19985,679,593'Method of fabricating a high resistance integrated circuit resistor'19975,677,567'Leads between chips assembly'19975,627,485'Voltage-independent super voltage detection circuit'19975,151,163'Electrochemical noise measurement technique for the determination of aluminum alloy pit initiation rates'19925,127,945'Effervescent cationic film forming corrosion inhibitor material for use in torpedo launcher tubes'19925,063,418'Optical non-linear artificial dielectrics'19915,057,343'Effervescent cationic film forming corrosion inhibitor material and process'19914,794,575'Submarine launched sea-state buoy (SLSSB)'19884,612,051'Water-based printing ink compositions containing a lignin acetate binder'19864,371,968'Monolithic injection laser arrays formed by crystal regrowth techniques'1983D0262086'Concrete outdoor cooking grill'1981D0250313'Concrete table'1978D0248784'Concrete basketball standard'1978D0247605'Concrete trash container'1978Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1978–2017Patents assigned to MILLER JAMES E (10)· patent assignee history
1978–1981Based in Birmingham, MI, US· patent location history
1988–1992Patents assigned to US NAVY (4)· patent assignee history
1988–1998Based in Middletown, RI, US· patent location history
1997–2012Patents assigned to MICRON TECHNOLOGY INC (54)· patent assignee history
1997–2012Based in Boise, ID, US· patent location history
2008–2019Patents assigned to SANDIA CORP (9)· patent assignee history
2008–2020Based in Albuquerque, NM, US· patent location history
2009–2014Based in Palm Beach Gardens, FL, US· patent location history
2018–2020Patents assigned to NAT TECH & ENG SOLUTIONS SANDIA LLC (7)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MICRON TECHNOLOGY INC | 54 | 1997–2012 |
| MILLER JAMES Eself | 10 | 1978–2017 |
| SANDIA CORP | 9 | 2008–2019 |
| NAT TECH & ENG SOLUTIONS SANDIA LLC | 7 | 2018–2020 |
| US NAVY | 4 | 1988–1992 |
Locations
| Location | Patents | Span |
|---|---|---|
| Boise, ID, US | 55 | 1997–2012 |
| Albuquerque, NM, US | 16 | 2008–2020 |
| Middletown, RI, US | 5 | 1988–1998 |
| Palm Beach Gardens, Florida, US | 2 | 2009–2014 |
| Birmingham, MI, US | 2 | 1978–1981 |