Inventor
Ryuichi Okamura
Inventor
Tokyo, JP
Overview
Patents· 15 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices35%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1025%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1020%
G01DMeasuring not specially adapted for a specific variable5%
G09BEducational or demonstration appliances5%
H03HImpedance networks, e.g. resonant circuits5%
H04RLoudspeakers, microphones, gramophone pick-ups or like acoustic electromechanical transducers5%
PatentTitleYear
10,862,448Piezoelectric thin film resonator, filter, and multiplexer20209,716,956'Piezoelectric thin film resonator and method of fabricating the same'20178,575,721'Semiconductor device'20138,546,851'Semiconductor integrated circuit device'20138,283,753'Semiconductor device'20127,602,064'Semiconductor device having an inspection hole striding a boundary'20097,420,190'Length measurement pattern, semiconductor device, and method of manufacturing a semiconductor device'20086,764,310'Apparatus for simulating ride on vehicle'20046,353,266'Semiconductor device having improved pad coupled to wiring on semiconductor substrate'20026,175,136'Method of forming CMOS device with improved lightly doped drain structure'20016,163,057'Field effect transistor with improved source/drain diffusion regions having an extremely small capacitance'20006,111,320'Semiconductor device having a barrier film for preventing penetration of moisture'20006,011,308'Semiconductor device having a barrier film formed to prevent the entry of moisture and method of manufacturing the same'20005,990,522'Field effect transistor with improved source/drain diffusion regions having an extremely small capacitance'19995,801,426'Field effect transistor with improved source/drain diffusion regions having an extremely small capacitance'1998Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1998–2002Patents assigned to NEC CORP (7)· patent assignee history
1998–2020Based in Tokyo, JP· patent location history
2004Based in Saitama, JP· patent location history
2008–2009Patents assigned to NEC ELECTRONICS CORP (2)· patent assignee history
2008–2013Based in Kanagawa, JP· patent location history
2012–2013Patents assigned to OKAMURA RYUICHI (3)· patent assignee history
2012–2013Patents assigned to RENESAS ELECTRONICS CORP (3)· patent assignee history
2017–2020Patents assigned to TAIYO YUDEN KK (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| NEC CORP | 7 | 1998–2002 |
| OKAMURA RYUICHIself | 3 | 2012–2013 |
| RENESAS ELECTRONICS CORP | 3 | 2012–2013 |
| NEC ELECTRONICS CORP | 2 | 2008–2009 |
| TAIYO YUDEN KK | 2 | 2017–2020 |
Locations
| Location | Patents | Span |
|---|---|---|
| Tokyo, JP | 9 | 1998–2020 |
| Kanagawa, JP | 5 | 2008–2013 |
| Saitama, JP | 1 | 2004 |