LexDanaLexDanabeta
Inventor

Hidekazu Oda

Inventor
Tokyo, JP

Overview

74→
Patents
1989–2021
Patent span
Electricity
Primary field (CPC H)

Patents· 74 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary
H10DInorganic electric semiconductor devices38%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1024%
H10BElectronic memory devices13%
H01LSemiconductor devices11%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h107%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests5%
G11CStatic stores1%
B01LChemical or physical laboratory apparatus for general use1%
G01NInvestigating or analysing materials by determining their chemical or physical properties1%
PatentTitleYear
11,000,845Pipette tip mounting adaptor202110,756,115Semiconductor device and manufacturing method of the same202010,510,775Semiconductor device and manufacturing method of the same201910,121,705Semiconductor device and method of manufacturing the same201810,050,122Semiconductor device and manufacturing method of the same20189,966,452Semiconductor device having a field effect transistor formed on a silicon-on-insulator substrate and manufacturing method thereof20189,935,125Semiconductor device and manufacturing method of the same20189,847,417Semiconductor device including gate electrode for applying tensile stress to silicon substrate, and method of manufacturing the same20179,614,081'Semiconductor device including gate electrode for applying tensile stress to silicon substrate, and method of manufacturing the same'20179,508,598'Semiconductor device and manufacturing method of the same'20169,443,870'Semiconductor device and method of manufacturing the same'20169,412,867'Semiconductor device including gate electrode for applying tensile stress to silicon substrate, and method of manufacturing the same'20169,349,816'Method of manufacturing semiconductor device with offset sidewall structure'20169,287,259'Semiconductor integrated circuit device and method for manufacturing semiconductor integrated circuit device'20169,214,464'Method of manufacturing semiconductor device with offset sidewall structure'20159,209,191'Semiconductor device including gate electrode for applying tensile stress to silicon substrate, and method of manufacturing the same'20159,184,053'Semiconductor device and method of manufacturing the same'20159,166,041'Semiconductor device and method of manufacturing the same'20158,987,081'Method of manufacturing semiconductor device with offset sidewall structure'20158,859,360'Method of manufacturing semiconductor device with offset sidewall structure'20148,809,186'Semiconductor device including gate electrode for applying tensile stress to silicon substrate, and method of manufacturing the same'20148,642,418'Method of manufacturing semiconductor device with offset sidewall structure'20148,586,475'Semiconductor device including gate electrode for applying tensile stress to silicon substrate, and method of manufacturing the same'20138,541,272'Method of manufacturing semiconductor device with offset sidewall structure'20138,415,213'Method of manufacturing semiconductor device with offset sidewall structure'20138,372,747'Semiconductor device including gate electrode for applying tensile stress to silicon substrate, and method of manufacturing the same'20137,998,802'Method of manufacturing semiconductor device with offset sidewall structure'20117,960,281'Semiconductor device including gate electrode for applying tensile stress to silicon substrate, and method of manufacturing the same'20117,563,663'Method of manufacturing semiconductor device with offset sidewall structure'20097,531,402'Method of manufacturing semiconductor device with offset sidewall structure'20097,470,618'Semiconductor device including gate electrode for applying tensile stress to silicon substrate, and method of manufacturing the same'20087,220,637'Method of manufacturing semiconductor device with offset sidewall structure'20077,183,204'Semiconductor device including gate electrode for applying tensile stress to silicon substrate, and method of manufacturing the same'20077,170,109'Heterojunction semiconductor device with element isolation structure'20076,906,393'Semiconductor device including gate electrode for applying tensile stress to silicon substrate, and method of manufacturing the same'20056,872,642'Manufacturing method of semiconductor device'20056,838,747'Semiconductor device having resistive element formed of semiconductor film'20056,835,610'Method of manufacturing semiconductor device having gate electrode with expanded upper portion'20046,740,939'Semiconductor device and manufacturing method thereof'20046,734,523'Semiconductor device including a well divided into a plurality of parts by a trench'20046,600,195'Semiconductor device'20036,521,527'Semiconductor device and method of fabricating the same'20036,521,519'MIS transistor and manufacturing method thereof'20036,518,623'Semiconductor device having a buried-channel MOS structure'20036,506,651'Semiconductor device and manufacturing method thereof'20036,483,133'EEPROM with high channel hot carrier injection efficiency'20026,475,844'Field effect transistor and method of manufacturing same'20026,469,347'Buried-channel semiconductor device, and manufacturing method thereof'20026,380,036'Semiconductor device and method of manufacturing the same'20026,359,321'MIS transistor and method of fabricating the same'20026,335,549'EEPROM with high channel hot carrier injection efficiency'20026,335,252'Semiconductor device manufacturing method'20026,300,664'Semiconductor device and method of fabricating the same'20016,239,471'MIS transistor and manufacturing method thereof'20016,235,564'Method of manufacturing MISFET'20016,180,519'Method of forming a layered wiring structure including titanium silicide'20016,162,668'Method of manufacturing a semiconductor device having a lightly doped contact impurity region surrounding a highly doped contact impurity region'20006,153,910'Semiconductor device with nitrogen implanted channel region'20006,130,463'Field effect transistor and method of manufacturing same'20006,107,156'Silicide layer forming method and semiconductor integrated circuit'20006,040,629'Semiconductor integrated circuit having silicided elements of short length'20005,978,294'Memory cell evaluation semiconductor device, method of fabricating the same and memory cell evaluation method'19995,950,098'Manufacturing method of a semiconductor device with a silicide layer'19995,945,710'Semiconductor device with doped contact impurity regions having particular doping levels'19995,837,606'Semiconductor device having internal wire and method of fabricating the same'19985,801,425'Semiconductor device having a wiring layer including a TISI2, film of the C49 or C54 structure'19985,710,438'Semiconductor device with a silicide layer'19985,557,129'Semiconductor MOSFET device having a shallow nitrogen implanted channel region'19965,550,409'Semiconductor device having internal wire and method of fabricating the same'19965,270,242'Method for fabricatins dynamic random access memory device having a capacitor for storing impact ionization charges'19935,218,217'Dynamic random access memory device and method of manufacturing'19934,987,092'Process for manufacturing stacked semiconductor devices'19914,984,199'Semiconductor memory cells having common contact hole'19914,887,137'Semiconductor memory device'1989

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1989–2003Patents assigned to MITSUBISHI ELECTRIC CORP (34)· patent assignee history
1989–2003Based in Hyogo, JP· patent location history
1998–2018Based in Tokyo, JP· patent location history
2004–2009Patents assigned to RENESAS TECH CORP (12)· patent assignee history
2011–2020Patents assigned to RENESAS ELECTRONICS CORP (27)· patent assignee history
2013–2016Patents assigned to ODA HIDEKAZU (3)· patent assignee history
2013Patents assigned to SAYAMA HIROKAZU (2)· patent assignee history
2015–2020Based in Kanagawa, JP· patent location history
2015–2018Based in Kawasaki, JP· patent location history
2021Based in Saitama, JP· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
MITSUBISHI ELECTRIC CORP341989–2003
RENESAS ELECTRONICS CORP272011–2020
RENESAS TECH CORP122004–2009
ODA HIDEKAZUself32013–2016
SAYAMA HIROKAZU22013
Locations
LocationPatentsSpan
Tokyo, JP471998–2018
Hyogo, JP161989–2003
Kanagawa, JP72015–2020
Kawasaki, JP22015–2018
Saitama, JP12021