Inventor
Aditya Ramamoorthy
Inventor
Ames, IA, US
Overview
Patents· 21 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores36%
H03MCoding33%
G06FElectric digital data processing23%
H04LTransmission of digital information, e.g. telegraphic communication5%
H04JMultiplex communication3%
PatentTitleYear
9,053,051'Multi-level memory controller with probability-distribution-based encoding'20159,009,560'Apparatus for encoding and decoding using sparse matrices'20158,869,014'Multi-level signal memory with LDPC and interleaving'20148,856,622'Apparatus and method for encoding data for storage in multi-level nonvolatile memory'20148,762,809'LDPC codes and expansion method'20148,693,275'Method and apparatus for calibrating a read/write channel in a memory arrangement'20148,677,215'Method and system for error correction in flash memory'20148,583,991'High density multi-level memory'20138,531,903'Method and apparatus for calibrating a read/write channel in a memory arrangement'20138,489,960'LDPC codes and expansion method'20138,473,812'Method and system for error correction in flash memory'20138,363,501'Method and apparatus for calibrating a read/write channel in a memory arrangement'20138,281,213'LDPC codes and expansion method'20128,219,886'High density multi-level memory'20127,971,130'Multi-level signal memory with LDPC and interleaving'20117,936,630'Method and apparatus for calibrating a read/write channel in a memory arrangement'20117,904,792'Apparatus and method for transmitting/receiving signal in a communication system'20117,869,344'1+N network protection for mesh networks: network coding-based protection using P-cycles and protection paths'20117,844,879'Method and system for error correction in flash memory'20107,774,675'LDPC codes and expansion method'20107,649,793'Channel estimation for multi-level memories using pilot signals'2010Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2010–2015Patents assigned to MARVELL INT LTD (13)· patent assignee history
2010–2015Patents assigned to MARVELL WORLD TRADE LTD (6)· patent assignee history
2010–2015Based in Ames, IA, US· patent location history
2010–2014Based in Santa Clara, CA, US· patent location history
2012–2014Patents assigned to RAMAMOORTHY ADITYA (7)· patent assignee history
2012–2013Patents assigned to WU ZINING (5)· patent assignee history
2012–2013Patents assigned to BURD GREGORY (3)· patent assignee history
2014Based in Redondo Beach, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MARVELL INT LTD | 13 | 2010–2015 |
| RAMAMOORTHY ADITYAself | 7 | 2012–2014 |
| MARVELL WORLD TRADE LTD | 6 | 2010–2015 |
| WU ZINING | 5 | 2012–2013 |
| BURD GREGORY | 3 | 2012–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Ames, IA, US | 15 | 2010–2015 |
| Santa Clara, California, US | 5 | 2010–2014 |
| Redondo Beach, California, US | 1 | 2014 |