Inventor
Ko Yoshikawa
Inventor
Tokyo, JP
Overview
Patents· 4 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing60%
H10DInorganic electric semiconductor devices20%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1020%
PatentTitleYear
7,617,466'Circuit conjunctive normal form generating method, circuit conjunctive normal form generating device, hazard check method and hazard check device'20097,028,273'Delay optimization designing system and delay optimization designing method for a logic circuit and control program'20066,870,199'Semiconductor device having an electrode overlaps a short carrier lifetime region'20056,243,852'Method of and an apparatus for logic circuit synthesis'2001Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2001–2009Patents assigned to NEC CORP (3)· patent assignee history
2001–2009Based in Tokyo, JP· patent location history
2005Patents assigned to FUJI ELECTRIC CO LTD (1)· patent assignee history
2005Based in Nagano, JP· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| NEC CORP | 3 | 2001–2009 |
| FUJI ELECTRIC CO LTD | 1 | 2005 |
Locations
| Location | Patents | Span |
|---|---|---|
| Tokyo, JP | 3 | 2001–2009 |
| Nagano, JP | 1 | 2005 |