Inventor
Jeff P. Erhardt
Inventor
San Jose, CA, US
Overview
Patents· 17 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices30%
H10BElectronic memory devices24%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1012%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1012%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests12%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices6%
G11CStatic stores3%
PatentTitleYear
7,476,604'Aggressive cleaning process for semiconductor device contact formation'20097,118,967'Protection of charge trapping dielectric flash memory devices from UV-induced charging in BEOL processing'20067,018,896'UV-blocking layer for reducing UV-induced charging of SONOS dual-bit flash memory devices in BEOL processing'20067,018,868'Disposable hard mask for memory bitline scaling'20066,987,048'Memory device having silicided bitlines and method of forming the same'20066,963,108'Recessed channel'20056,855,608'Method of fabricating a planar structure charge trapping memory cell array with rectangular gates and reduced bit line resistance'20056,835,662'Partially de-coupled core and periphery gate module process'20046,774,432'UV-blocking layer for reducing UV-induced charging of SONOS dual-bit flash memory devices in BEOL'20046,744,105'Memory array having shallow bit line with silicide contact portion and method of formation'20046,613,500'Reducing resist residue defects in open area on patterned wafer using trim mask'20036,576,548'Method of manufacturing a semiconductor device with reliable contacts/vias'20036,521,501'Method of forming a CMOS transistor having ultra shallow source and drain regions'20036,514,859'Method of salicide formation with a double gate silicide'20036,513,151'Full flow focus exposure matrix analysis and electrical testing for new product mask evaluation'20036,399,467'Method of salicide formation'20026,387,786'Method of salicide formation by siliciding a gate area prior to siliciding a source and drain area'2002Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2002–2009Patents assigned to ADVANCED MICRO DEVICES INC (16)· patent assignee history
2002–2009Based in San Jose, CA, US· patent location history
2006–2009Patents assigned to SPANSION LLC (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ADVANCED MICRO DEVICES INC | 16 | 2002–2009 |
| SPANSION LLC | 2 | 2006–2009 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 17 | 2002–2009 |