Inventor
Deepika Priyadarshini
Inventor
Guilderland, NY, US
Overview
Patents· 56 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices30%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1026%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1022%
H10DInorganic electric semiconductor devices14%
C23CCoating metallic material6%
H01BCables1%
B32BLayered products, i.e. products built-up of strata of flat or non-flat, e.g. cellular or honeycomb, form1%
PatentTitleYear
11,066,748Microwave plasma and ultraviolet assisted deposition apparatus and method for material deposition using the same202111,043,494Structure and method for equal substrate to channel height between N and P fin-FETs202110,770,347Interconnect structure202010,593,591Interconnect structure202010,580,740Low-temperature diffusion doping of copper interconnects independent of seed layer composition202010,428,428Microwave plasma and ultraviolet assisted deposition apparatus and method for material deposition using the same201910,381,348Structure and method for equal substrate to channel height between N and P fin-FETs201910,366,940Air gap and air spacer pinch off201910,325,806Copper interconnect structure with manganese oxide barrier layer201910,256,171Air gap and air spacer pinch off201910,242,865Robust high performance low hydrogen silicon carbon nitride (SiCNH) dielectrics for nano electronic devices201910,242,933Air gap and air spacer pinch off201910,236,176Robust high performance low hydrogen silicon carbon nitride (SiCNH) dielectrics for nano electronic devices201910,229,910Separate N and P fin etching for reduced CMOS device leakage201910,224,283Composite manganese nitride / low-k dielectric cap201910,224,241Copper interconnect structure with manganese oxide barrier layer201910,211,047Multilayer dielectric structures with graded composition for nano-scale semiconductor devices201910,192,829Low-temperature diffusion doping of copper interconnects independent of seed layer composition201910,177,076Air gap and air spacer pinch off201910,134,577Edge trim processes and resultant structures20189,960,117Air gap semiconductor structure with selective cap bilayer20189,947,581Method of forming a copper based interconnect structure20189,947,622Ultrathin superlattice of MnO/Mn/MnN and other metal oxide/metal/metal nitride liners and caps for copper low dielectric constant interconnects20189,947,579Copper interconnect structure with manganese oxide barrier layer20189,934,963Multilayer dielectric structures with graded composition for nano-scale semiconductor devices20189,793,193'Air gap and air spacer pinch off'20179,786,760'Air gap and air spacer pinch off'20179,754,891'Low-temperature diffusion doping of copper interconnects independent of seed layer composition'20179,735,005'Robust high performance low hydrogen silicon carbon nitride (SiCNH) dielectrics for nano electronic devices'20179,711,456'Composite manganese nitride/low-K dielectric cap'20179,711,507'Separate N and P fin etching for reduced CMOS device leakage'20179,711,455'Method of forming an air gap semiconductor structure with selective cap bilayer'20179,691,705'Ultrathin superlattice of MnO/Mn/MnN and other metal oxide/metal/metal nitride liners and caps for copper low dielectric constant interconnects'20179,620,481'Substrate bonding with diffusion barrier structures'20179,607,825'Hydrogen-free silicon-based deposited dielectric films for nano device fabrication'20179,601,371'Interconnect structure with barrier layer'20179,558,934'Hydrogen-free silicon-based deposited dielectric films for nano device fabrication'20179,558,935'Hydrogen-free silicon-based deposited dielectric films for nano device fabrication'20179,536,733'Hydrogen-free silicon-based deposited dielectric films for nano device fabrication'20179,472,503'Ultrathin superlattice of MnO/Mn/MnN and other metal oxide/metal/metal nitride liners and caps for copper low dielectric constant interconnects'20169,455,182'Interconnect structure with capping layer and barrier layer'20169,449,812'Hydrogen-free silicon-based deposited dielectric films for nano device fabrication'20169,449,810'Advanced ultra low k SiCOH dielectrics prepared by built-in engineered pore size and bonding structured with cyclic organosilicon precursors'20169,435,031'Microwave plasma and ultraviolet assisted deposition apparatus and method for material deposition using the same'20169,431,235'Multilayer dielectric structures with graded composition for nano-scale semiconductor devices'20169,412,629'Wafer bonding for 3D device packaging fabrication'20169,349,687'Advanced manganese/manganese nitride cap/etch mask for air gap formation scheme in nanocopper low-K interconnect'20169,312,224'Interconnect structure containing a porous low k interconnect dielectric/dielectric cap'20169,305,836'Air gap semiconductor structure with selective cap bilayer'20169,275,952'Ultrathin superlattice of MnO/Mn/MnN and other metal oxide/metal/metal nitride liners and caps for copper low dielectric constant interconnects'20169,214,332'Composite dielectric materials with improved mechanical and electrical properties'20159,209,017'Advanced ultra low k SiCOH dielectrics prepared by built-in engineered pore size and bonding structured with cyclic organosilicon precursors'20159,064,937'Substrate bonding with diffusion barrier structures'20159,028,628'Wafer-to-wafer oxide fusion bonding'20158,981,466'Multilayer dielectric structures for semiconductor nano-devices'20158,980,715'Multilayer dielectric structures for semiconductor nano-devices'2015Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2015–2021Patents assigned to IBM (52)· patent assignee history
2015–2021Based in Guilderland, NY, US· patent location history
2016–2018Patents assigned to GLOBALFOUNDRIES INC (3)· patent assignee history
2017–2019Based in Philadelphia, PA, US· patent location history
2017Based in Guilerland, NY, US· patent location history
2020Patents assigned to TESSERA INC (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 52 | 2015–2021 |
| GLOBALFOUNDRIES INC | 3 | 2016–2018 |
| TESSERA INC | 2 | 2020 |
Locations
| Location | Patents | Span |
|---|---|---|
| Guilderland, New York, US | 53 | 2015–2021 |
| Philadelphia, Pennsylvania, US | 2 | 2017–2019 |
| Guilerland, New York, US | 1 | 2017 |