Inventor

Suresh K. Marisetty

Inventor

San Jose, CA, US

Overview

26→

Patents

1993–2011

Patent span

Physics

Primary field (CPC G)

Patents· 26 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing81%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use10%

H04LTransmission of digital information, e.g. telegraphic communication6%

G11CStatic stores3%

PatentTitleYear

7,904,751'System abstraction layer, processor abstraction layer, and operating system error handling'2011 7,721,148'Method and apparatus for redirection of machine check interrupts in multithreaded systems'2010 7,587,639'System and method for error injection using a flexible program interface field'2009 7,546,487'OS and firmware coordinated error handling using transparent firmware intercept and firmware services'2009 7,533,300'Configurable error handling apparatus and methods to operate the same'2009 7,502,959'Error correction apparatus, systems, and methods'2009 7,353,433'Poisoned error signaling for proactive OS recovery'2008 7,308,610'Method and apparatus for handling errors in a processing system'2007 RE039837'Method and apparatus for adjusting a power consumption level based on the amount of time a processor clock is stopped'2007 7,117,396'Scalable CPU error recorder'2006 RE039284'Method and apparatus for reducing power consumption in a system using power management software capable of placing multiple configurable system devices in a reduced power consumption state'2006 6,754,828'Algorithm for non-volatile memory updates'2004 6,675,324'Rendezvous of processors with OS coordination'2004 6,622,260'System abstraction layer, processor abstraction layer, and operating system error handling'2003 6,047,355'Symmetric multiprocessing system with unified environment and distributed system functions'2000 5,925,117'Method and apparatus for enabling application programs to continue operation when an application resource is no longer present after undocking from a network'1999 5,809,340'Adaptively generating timing signals for access to various memory devices based on stored profiles'1998 5,793,961'Computer system with data conference capability'1998 5,768,598'Method and apparatus for sharing hardward resources in a computer system'1998 5,666,521'Method and apparatus for performing bit block transfers in a computer system'1997 5,590,342'Method and apparatus for reducing power consumption in a computer system using virtual device drivers'1996 5,590,312'Method and apparatus for emulating circuitry in a computer system using a system management interrupt'1996 5,574,868'Bus grant prediction technique for a split transaction bus in a multiprocessor computer system'1996 5,522,069'Symmetric multiprocessing system with unified environment and distributed system functions'1996 5,369,651'Multiplexed byte enable bus for partial word writes to ECC protected memory'1994 5,271,020'Bus stretching protocol for handling invalid data'1993

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1993–2011Patents assigned to INTEL CORP (24)· patent assignee history

1993–2011Based in San Jose, CA, US· patent location history

1996Patents assigned to ZENITH DATA SYSTEMS CORP (1)· patent assignee history

1998Patents assigned to PACKARD BELL NEC (1)· patent assignee history

2009–2010Based in Fremont, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
INTEL CORP	24	1993–2011
PACKARD BELL NEC	1	1998
ZENITH DATA SYSTEMS CORP	1	1996

Locations

Location	Patents	Span
San Jose, California, US	22	1993–2011
Fremont, California, US	4	2009–2010