Inventor
Sung-Feng Yeh
Inventor
Taipei, TW
Overview
Patents· 45 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices34%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1034%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1023%
H10DInorganic electric semiconductor devices3%
H05KPrinted circuits2%
G02BOptical elements, systems or apparatus1%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation1%
H10HInorganic light-emitting semiconductor devices having potential barriers1%
Y10TTechnical subjects covered by former us classification1%
PatentTitleYear
10,872,836Package structure for heat dissipation202010,867,966Package structure, package-on-package structure and method of fabricating the same202010,867,929Semiconductor structures and methods of forming the same202010,867,879Integrated circuit package and method202010,854,574Forming metal bonds with recesses202010,840,217Stacked chip package and methods of manufacture thereof202010,797,015Method of manufacturing 3DIC structure202010,784,219Semiconductor device and method of manufacturing202010,756,010Semiconductor device packaging structure having through interposer vias and through substrate vias202010,685,910Packages with Si-substrate-free interposer and method forming same202010,685,935Forming metal bonds with recesses202010,685,911Semiconductor package and manufacturing method of the same202010,672,674Method of forming semiconductor device package having testing pads on a topmost die202010,672,754Semiconductor component, package structure and manufacturing method thereof202010,658,333Package structure and method of fabricating the same202010,622,327Method for manufacturing semiconductor structure202010,541,227System on integrated chips and methods of forming same202010,535,6313D Chip-on-wager-on-substrate structure with via last process202010,510,718Semiconductor structure and manufacturing method thereof201910,510,650Method of manufacturing semiconductor device packaging structure having through interposer vias and through substrate vias201910,475,7623DIC structure and method of manufacturing the same201910,381,298Packages with Si-substrate-free interposer and method forming same201910,319,707Semiconductor component, package structure and manufacturing method thereof201910,290,571Packages with si-substrate-free interposer and method forming same201910,163,750Package structure for heat dissipation201810,163,859Structure and formation method for chip package201810,163,799Semiconductor structure and method of manufacturing the same201810,157,890Semiconductor structure and method of manufacturing the same201810,157,8823D chip-on-wafer-on-substrate structure with via last process201810,096,571Chip-on-wafer package and method of forming same201810,074,629System on integrated chips and methods of forming same201810,026,7163DIC formation with dies bonded to formed RDLs201810,014,271Semiconductor structure and method of manufacturing the same20189,899,355'Three-dimensional integrated circuit structure'20189,875,982Semiconductor device and manufacturing method thereof20189,859,254'Semiconductor structure and a manufacturing method thereof'20189,806,055'Chip-on-wafer package and method of forming same'20179,754,918'3D chip-on-wafer-on-substrate structure with via last process'20179,741,694'Semiconductor structure and method of manufacturing the same'20179,620,488'Three-dimensional integrated circuit structure and bonded structure'20179,548,274'Reticle for non-rectangular die'20179,524,959'System on integrated chips and methods of forming same'20169,508,703'Stacked dies with wire bonds and method'20169,331,021'Chip-on-wafer package and method of forming same'20168,042,445'Cutting mold for rigid-flexible circuit board and method for forming the same'2011Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2011Patents assigned to NAN YA PRINTED CIRCUIT BOARD (1)· patent assignee history
2011Based in Taoyuan County, TW· patent location history
2016–2020Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (43)· patent assignee history
2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (1)· patent assignee history
2016–2020Based in Taipei, TW· patent location history
2018Based in Hsinchu, TW· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG CO LTD | 43 | 2016–2020 |
| NAN YA PRINTED CIRCUIT BOARD | 1 | 2011 |
| TAIWAN SEMICONDUCTOR MFG | 1 | 2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| Taipei, TW | 43 | 2016–2020 |
| Hsinchu, TW | 1 | 2018 |
| Taoyuan County, TW | 1 | 2011 |