Inventor
PERNG-FEI YUH
Inventor
US
Overview
Patents· 50 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores32%
H10DInorganic electric semiconductor devices17%
H10BElectronic memory devices14%
H01LSemiconductor devices10%
H03KPulse technique6%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h105%
H01JElectric discharge tubes or discharge lamps4%
H10NElectric solid-state devices not otherwise provided for4%
B82YSpecific uses or applications of nanostructures3%
G05FSystems for regulating electric or magnetic variables3%
PatentTitleYear
12,542,254Grid structures of ion beam etching (IBE) systems202612,513,912Method for fabricating an integrated circuit comprising devices on opposing sides of a substrate202512,424,257Memory devices with dual-side access circuits and methods for operating the same202512,417,796Ferroelectric field-effect transistor (FeFET) memory202512,412,620Second word line combined with y-mux signal in high voltage memory program202512,387,968Radical-activated etching of metal oxides202512,386,374Push-pull low-dropout (LDO) voltage regulator202512,389,806MRAM cell and MRAM202512,380,950Non-volatile static random access memory (NVSRAM) with multiple magnetic tunnel junction cells202512,347,505Memory device and operating method of the same202512,284,804Memory devices, semiconductor devices, and methods of operations a memory device202512,254,923Nonvolatile SRAM202512,243,599Merged bit lines for high density memory array202512,230,338Semiconductor memory devices with diode-connected MOS202512,218,015Interferometer systems and methods for real time etch process compensation control202512,217,822Memory device with source line control202512,211,918Nanostructured channel regions for semiconductor devices202512,210,368Bias generating devices and methods for generating bias202512,190,986Sense amplifier for coupling effect reduction202512,190,949Memory circuit and method of operating the same202512,183,397Memory circuits and devices, and methods thereof202412,148,487High-density and high-voltage-tolerable pure core memory cell202412,094,558Multiple stack high voltage circuit for memory202412,087,378Bit selection for power reduction in stacking structure during memory programming202412,027,583Gate structures for semiconductor devices202412,002,528Memory device and operating method of the same202411,984,164Non-volatile static random access memory (nvSRAM) with multiple magnetic tunnel junction cells202411,961,706Grid structures of ion beam etching (IBE) systems202411,963,463MRAM cell and MRAM202411,953,927Bias generating devices and methods for generating bias202411,955,190Merged bit lines for high density memory array202411,955,191Semiconductor memory devices with diode-connected MOS202411,903,188Memory devices, semiconductor devices, and methods of operating a memory device202411,881,242Ferroelectric field-effect transistor (FeFET) memory202411,869,954Nanostructured channel regions for semiconductor devices202411,810,635Sense amplifier for coupling effect reduction202311,776,595Memory device with source line control202311,763,875Second word line combined with Y-MUX signal in high voltage memory program202311,735,280Memory device and operating method of the same202311,688,481Semiconductor memory devices with diode-connected MOS202311,682,433Multiple stack high voltage circuit for memory202311,676,676Merged bit lines for high density memory array202311,664,081Bit selection for power reduction in stacking structure during memory programming202311,657,873Non-volatile static random access memory (nvSRAM) with multiple magnetic tunnel junction cells202311,651,819Memory circuit and method of operating the same202311,601,117Sense amplifier for coupling effect reduction202311,545,218Nonvolatile SRAM202311,450,370Ferroelectric field-effect transistor (FeFET) memory202211,322,680MRAM cell, MRAM and IC with MRAM202211,276,604Radical-activated etching of metal oxides2022Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2022–2026Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (50)· patent assignee history
2022–2026Based in US· patent location history
2023–2025Based in TW· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG CO LTD | 50 | 2022–2026 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 36 | 2022–2026 |
| TW | 14 | 2023–2025 |