Inventor
Michael L. Ziegler
Inventor
Whitinsville, MA, US
Overview
Patents· 45 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing65%
H04LTransmission of digital information, e.g. telegraphic communication23%
G01NInvestigating or analysing materials by determining their chemical or physical properties4%
B01LChemical or physical laboratory apparatus for general use2%
G06QInformation and communication technology [ict] specially adapted for administrative, commercial, financial, managerial or supervisory purposes2%
G11CStatic stores2%
H04WWireless communication networks2%
PatentTitleYear
9,426,083'Consistency checking for credit-based control of data communications'20169,237,082'Packet descriptor trace indicators'20169,172,653'Sending request messages to nodes indicated as unresolved'20159,112,820'Delay queues based on delay remaining'20158,940,252'Rack apparatus for a sample distribution system'20158,908,711'Target issue intervals'20148,879,571'Delays based on packet sizes'20148,830,838'Node interface indicators'20148,689,049'Corrective actions based on probabilities'20148,539,113'Indicators for streams associated with messages'20138,537,859'Reassembly of mini-packets in a buffer'20138,209,236'Merchandise tracking and ordering system'20128,046,569'Processing element having dual control stores to minimize branch latency'20117,771,659'Arrangement and method for the analysis of body fluids'20107,478,262'Method for allowing distributed high performance coherent memory with full error containment'20097,346,802'Routing communications to a storage area network'20087,191,319'System and method for preloading cache memory in response to an occurrence of a context switch'20076,925,535'Program control flow conditioned on presence of requested data in cache memory'20056,880,153'Method and apparatus for varying the level of correctness checks executed when performing correctness checks opportunistically using spare instruction slots'20056,874,138'Method and apparatus for resuming execution of a failed computer program'20056,708,288'Compiler-based checkpointing for support of error recovery'20046,651,193'Method for allowing distributed high performance coherent memory with full error containment'20036,473,845'System and method for dynamically updating memory address mappings'20026,304,932'Queue-based predictive flow control mechanism with indirect determination of queue fullness'20016,286,095'Computer apparatus having special instructions to force ordered load and store operations'20016,199,144'Method and apparatus for transferring data in a computer system'20016,182,176'Queue-based predictive flow control mechanism'20016,128,706'Apparatus and method for a load bias--load with intent to semaphore'20005,784,708'Translation mechanism for input/output addresses'19985,737,757'Cache tag system for use with multiple processors including the most recently requested processor identification'19985,586,297'Partial cache line write transactions in a computing system with a write back cache'19965,535,352'Access hints for input/output address translation mechanisms'19965,530,933'Multiprocessor system for maintaining cache coherency by checking the coherency in the order of the transactions being issued on the bus'19965,528,766'Multiple arbitration scheme'19965,519,838'Fast pipelined distributed arbitration scheme'19965,515,522'Coherence index generation for use by an input/output adapter located outside of the processor to detect whether the updated version of data resides within the cache'19965,133,059'Computer with multiple processors having varying priorities for access to a multi-element memory'19924,794,521'Digital computer with cache capable of concurrently handling multiple accesses from parallel processors'19884,783,736'Digital computer with multisection cache'19884,622,630'Data processing system having unique bus control protocol'19864,513,372'Universal memory'19854,493,033'Dual port cache with interleaved read accesses during alternate half-cycles and simultaneous writing'19854,398,243'Data processing system having a unique instruction processor system'19834,386,399'Data processing system'19834,380,812'Refresh and error detection and correction technique for a data processing system'1983Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1983–1986Patents assigned to DATA GENERAL CORP (6)· patent assignee history
1983–2001Based in Whitinsville, MA, US· patent location history
1988–1992Patents assigned to ALLIANT COMPUTER SYSTEMS (3)· patent assignee history
1996–2002Patents assigned to HEWLETT PACKARD CO (12)· patent assignee history
2000–2009Based in Campbell, CA, US· patent location history
2003–2015Patents assigned to HEWLETT PACKARD DEVELOPMENT CO (17)· patent assignee history
2010–2015Based in Schwaikheim, DE· patent location history
2011–2016Based in Roseville, CA, US· patent location history
2012Based in Rolling Hills, CA, US· patent location history
2013–2016Patents assigned to ZIEGLER MICHAEL L (10)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| HEWLETT PACKARD DEVELOPMENT CO | 17 | 2003–2015 |
| HEWLETT PACKARD CO | 12 | 1996–2002 |
| ZIEGLER MICHAEL Lself | 10 | 2013–2016 |
| DATA GENERAL CORP | 6 | 1983–1986 |
| ALLIANT COMPUTER SYSTEMS | 3 | 1988–1992 |
Locations
| Location | Patents | Span |
|---|---|---|
| Whitinsville, Massachusetts, US | 20 | 1983–2001 |
| Roseville, California, US | 11 | 2011–2016 |
| Campbell, California, US | 11 | 2000–2009 |
| Schwaikheim, DE | 2 | 2010–2015 |
| Rolling Hills, California, US | 1 | 2012 |