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Inventor

Xiaobin Wang

Inventor
Chanhassen, MN, US

Overview

165→
Patents
1999–2020
Patent span
Electricity
Primary field (CPC H)

Patents· 165 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary
G11CStatic stores19%
H10DInorganic electric semiconductor devices16%
H01LSemiconductor devices11%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h108%
H10NElectric solid-state devices not otherwise provided for6%
H10BElectronic memory devices5%
H01FMagnets5%
B82YSpecific uses or applications of nanostructures4%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h104%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests2%
PatentTitleYear
10,684,778Data updating in non-volatile memory202010,665,551Trench MOSFET device and the preparation method thereof202010,593,759Nanotube semiconductor devices202010,559,624Selector device having asymmetric conductance for memory applications202010,535,764Device and fabrication of MOS device with island region202010,519,561Steering gear assembly and method of manufacturing same201910,418,899MOSFET switch circuit for slow switching application201910,396,158Termination structure for nanotube semiconductor devices201910,224,367Selector device incorporating conductive clusters for memory applications201910,153,017Method for sensing memory element coupled to selector device201810,074,742MOS device with island region201810,062,755Nanotube termination structure for power semiconductor devices201810,032,728Trench MOSFET device and the preparation method thereof201810,008,540Spin-orbitronics device and applications thereof20189,997,593Power trench MOSFET with improved unclamped inductive switching (UIS) performance and preparation method thereof20189,960,237Termination structure with multiple embedded potential spreading capacitive structures for trench MOSFET20189,899,474'Nanotube semiconductor devices'20189,871,190'Magnetic random access memory with ultrathin reference layer'20189,871,191'Magnetic random access memory with ultrathin reference layer'20189,831,421Magnetic memory element with composite fixed layer20179,704,948'Power trench MOSFET with improved unclamped inductive switching (UIS) performance and preparation method thereof'20179,704,955'Nanotube semiconductor devices'20179,647,202'Magnetic random access memory with perpendicular enhancement layer'20179,647,032'Spin-orbitronics device and applications thereof'20179,627,526'Assymetric poly gate for optimum termination design in trench power MOSFETs'20179,586,570'Methods and system for verifying a brake system in a vehicle'20179,570,404'Flexible Crss adjustment in a SGT MOSFET to smooth waveforms and to avoid EMI in DC-DC application'20179,559,144'Magnetic random access memory element having tantalum perpendicular enhancement layer'20179,548,074'Perpendicular magnetic recording media with magnetic anisotropy gradient and local exchange coupling'20179,548,334'Magnetic tunnel junction with perpendicular enhancement layer and thin reference layer'20179,543,506'Magnetic random access memory with tri-layer reference layer'20179,502,503'Nanotube semiconductor devices'20169,450,843'Method for indicating port states and switch'20169,443,577'Voltage-switched magnetic random access memory (MRAM) and method for using the same'20169,431,495'Method of forming SGT MOSFETs with improved termination breakdown voltage'20169,356,022'Semiconductor device with termination structure for power MOSFET applications'20169,349,796'Nanotube semiconductor devices'20169,306,154'Magnetic random access memory with perpendicular enhancement layer'20169,245,949'Nanotube semiconductor devices'20169,236,450'Fabrication of MOS device with schottky barrier controlling layer'20169,231,027'Magnetic random access memory having perpendicular enhancement layer and interfacial anisotropic free layer'20169,214,545'Dual gate oxide trench MOSFET with channel stop trench'20159,166,143'Magnetic random access memory with multiple free layers'20159,149,783'Device for producing ethoxylation derivatives'20159,128,821'Data updating in non-volatile memory'20159,105,494'Termination trench for power MOSFET applications'20159,093,521'Enhancing Schottky breakdown voltage (BV) without affecting an integrated MOSFET-Schottky device layout'20159,087,593'Random bit generator that applies alternating current (AC) to magnetic tunnel junction to generate a random bit'20159,082,951'Magnetic random access memory with perpendicular enhancement layer'20159,070,855'Magnetic random access memory having perpendicular enhancement layer'20159,030,864'Magnetic tunnel junction with electronically reflective insulative spacer'20159,029,236'Termination structure with multiple embedded potential spreading capacitive for trench MOSFET and method'20158,962,164'Perpendicular magnetic recording media with magnetic anisotropy gradient and local exchange coupling'20158,952,205'Method for producing methoxypolyethylene glycols'20158,928,031'Nanotube semiconductor devices'20158,928,079'MOS device with low injection diode'20158,929,016'Heater assembly and method of heating'20158,907,416'Dual gate oxide trench MOSFET with channel stop trench'20148,809,143'Fabrication of MOS device with schottky barrier controlling layer'20148,802,530'MOSFET with improved performance through induced net charge region in thick bottom insulator'20148,792,264'Method of switching out-of-plane magnetic tunnel junction cells'20148,780,619'Magnetic memory element with multi-domain storage layer'20148,742,518'Magnetic tunnel junction with free layer having exchange coupled magnetic elements'20148,729,601'Nanotube semiconductor devices'20148,728,890'Fabrication of MOS device with integrated Schottky diode in active region contact trench'20148,697,520'Method of forming an asymmetric poly gate for optimum termination design in trench power MOSFETS'20148,692,322'Flexible Crss adjustment in a SGT MOSFET to smooth waveforms and to avoid EMI in DC-DC application'20148,642,429'Wide and deep oxide trench in a semiconductor substrate with interspersed vertical oxide ribs'20148,637,368'Fabrication of MOS device with varying trench depth'20148,598,623'Nanotube semiconductor devices and nanotube termination structures'20138,553,454'Predictive thermal preconditioning and timing control for non-volatile memory cells'20138,526,215'Spatial correlation of reference cells in resistive memory array'20138,519,495'Single line MRAM'20138,508,988'Magnetic tunnel junction with compensation element'20138,508,973'Method of switching out-of-plane magnetic tunnel junction cells'20138,501,330'Perpendicular magnetic recording media with magnetic anisotropy gradient and local exchange coupling'20138,493,555'Distributed Brillouin sensing systems and methods using few-mode sensing optical fiber'20138,493,556'Distributed brillouin sensing systems and methods using few-mode sensing optical fiber'20138,495,118'Tunable random bit generator with magnetic tunnel junction'20138,481,181'Exchange coupled magnetic elements'20138,482,971'Diode assisted switching spin-transfer torque memory unit'20138,482,967'Magnetic memory element with multi-domain storage layer'20138,471,332'Enhancing Schottky breakdown voltage (BV) without affecting an integrated MOSFET-Schottky device layout'20138,450,794'MOS device with varying contact trench lengths'20138,400,825'Magnetic field assisted stram cells'20138,399,925'Termination structure with multiple embedded potential spreading capacitive structures for trench MOSFET and method'20138,394,702'Method for making dual gate oxide trench MOSFET with channel stop using three or four masks process'20138,391,055'Magnetic tunnel junction and memristor apparatus'20138,390,058'Configurations and methods for manufacturing devices with trench-oxide-nano-tube super-junctions'20138,362,547'MOS device with Schottky barrier controlling layer'20138,354,316'Reduced mask configuration for power mosfets with electrostatic discharge (ESD) circuit protection'20138,320,169'Asymmetric write current compensation'20128,299,494'Nanotube semiconductor devices'20128,289,758'Magnetic tunnel junction with electronically reflective insulative spacer'20128,289,759'Non-volatile memory cell with precessional switching'20128,289,756'Non volatile memory including stabilizing structures'20128,283,723'MOS device with low injection diode'20128,270,204'Domain wall movement on magnetic strip tracks'20128,253,192'MOS device with varying trench depth'20128,247,329'Nanotube semiconductor devices'20128,247,297'Method of filling large deep trench with high quality oxide for semiconductor devices'20128,223,532'Magnetic field assisted STRAM cells'20128,213,222'Magnetic tunnel junction with compensation element'20128,213,215'Resistive sense memory calibration for self-reference read method'20128,203,862'Voltage reference generation with selectable dummy regions'20128,203,899'Memory cell with proportional current self-reference sensing'20128,199,562'Memory cell with enhanced read and write sense margins'20128,199,569'Diode assisted switching spin-transfer torque memory unit'20128,198,660'Multi-bit STRAM memory cells'20128,194,444'Spin-transfer torque memory self-reference read method'20128,154,914'Predictive thermal preconditioning and timing control for non-volatile memory cells'20128,139,397'Spatial correlation of reference cells in resistive memory array'20128,107,282'Asymmetric write current compensation'20128,105,895'Enhancing Schottky breakdown voltage (BV) without affecting an integrated MOSFET-Schottky device layout'20128,102,691'Magnetic tracks with domain wall storage anchors'20128,093,651'MOS device with integrated schottky diode in active region contact trench'20128,059,453'Magnetic tunnel junction and memristor apparatus'20118,054,678'Stuck-at defect condition repair for a non-volatile memory cell'20118,054,675'Variable write and read methods for resistive random access memory'20118,049,315'Use of discrete conductive layer in semiconductor device to re-route bonding wires for semiconductor device package'20118,048,545'Perpendicular magnetic recording media with magnetic anisotropy gradient and local exchange coupling'20118,045,370'Memory self-reference read and write assist methods'20118,023,316'Magnetic tunnel junction with compensation element'20117,961,509'Spin-transfer torque memory self-reference read and write assist methods'20117,952,139'Enhancing Schottky breakdown voltage (BV) without affecting an integrated MOSFET-Schottky device layout'20117,952,917'Variable write and read methods for resistive random access memory'20117,948,029'MOS device with varying trench depth'20117,944,742'Diode assisted switching spin-transfer torque memory unit'20117,944,730'Write method with voltage line tuning'20117,940,551'STRAM with electronically reflective insulative spacer'20117,936,592'Non-volatile memory cell with precessional switching'20117,916,528'Predictive thermal preconditioning and timing control for non-volatile memory cells'20117,910,486'Method for forming nanotube semiconductor devices'20117,898,838'Resistive sense memory calibration for self-reference read method'20117,898,844'Magnetic tunnel junction and memristor apparatus'20117,894,250'Stuck-at defect condition repair for a non-volatile memory cell'20117,884,454'Use of discrete conductive layer in semiconductor device to re-route bonding wires for semiconductor device package'20117,881,096'Asymmetric write current compensation'20117,876,604'Stram with self-reference read scheme'20117,876,595'Magnetic shift register as counter and data storage device'20117,876,599'Spatial correlation of reference cells in resistive memory array'20117,852,665'Memory cell with proportional current self-reference sensing'20107,852,660'Enhancing read and write sense margins in a resistive sense element'20107,853,388'Devices, systems, and methods for controlling a braking system'20107,846,564'Perpendicular magnetic recording media with magnetic anisotropy/coercivity gradient and local exchange coupling'20107,834,385'Multi-bit STRAM memory cells'20107,826,255'Variable write and read methods for resistive random access memory'20107,826,260'Spin-transfer torque memory self-reference read and write assist methods'20107,825,431'Reduced mask configuration for power MOSFETs with electrostatic discharge (ESD) circuit protection'20107,826,256'STRAM with compensation element'20107,813,168'Spin-transfer torque memory self-reference read and write assist methods'20107,804,709'Diode assisted switching spin-transfer torque memory unit'20107,800,938'Oscillating current assisted spin torque magnetic memory'20107,776,963'Acrylic adhesives for metal bonding applications'20107,479,528'Acrylate/methacrylate adhesives initiated by chlorosulfonated polymer'20097,348,385'Acrylate/methacrylate adhesives initiated by chlorosulfonated polymer'20087,308,352'Enhanced braking system and method'20077,034,476'System and method for providing automatic power control and torque boost'20066,885,930'System and method for slip slide control'20056,512,043'Two-part structural adhesive having long working time'20036,498,210'Silylated polyurethanes for adhesives and sealants with improved mechanical properties'20026,401,925'Fast-cure silylated polymer adhesive'20026,124,387'Fast-cure silylated polymer adhesive'20006,048,579'Primer for improving the bonding of adhesives to nonporous substrates'20006,008,305'Primer for improving the bonding of adhesives to nonporous substrates'1999

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2005–2010Based in Alpharetta, GA, US· patent location history
2010–2020Patents assigned to SEAGATE TECHNOLOGY LLC (69)· patent assignee history
2010–2020Based in Chanhassen, MN, US· patent location history
2010–2020Based in San Jose, CA, US· patent location history
2011–2017Patents assigned to WANG XIAOBIN (59)· patent assignee history
2011–2020Patents assigned to ALPHA & OMEGA SEMICONDUCTOR (51)· patent assignee history
2011–2015Patents assigned to CHEN YIRAN (19)· patent assignee history
2011–2013Based in Chanhasssen, MN, US· patent location history
2012–2017Patents assigned to BHALLA ANUP (19)· patent assignee history
2015–2020Based in Fremont, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
SEAGATE TECHNOLOGY LLC692010–2020
WANG XIAOBINself592011–2017
ALPHA & OMEGA SEMICONDUCTOR512011–2020
BHALLA ANUP192012–2017
CHEN YIRAN192011–2015
Locations
LocationPatentsSpan
Chanhassen, Minnesota, US642010–2020
San Jose, California, US562010–2020
Fremont, California, US182015–2020
Chanhasssen, Minnesota, US42011–2013
Alpharetta, Georgia, US42005–2010