Inventor
Gary K. Giust
Inventor
Cupertino, CA, US
Overview
Patents· 19 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices31%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1023%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests12%
G01RMeasuring electric variables8%
G11CStatic stores8%
G06QInformation and communication technology [ict] specially adapted for administrative, commercial, financial, managerial or supervisory purposes4%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses4%
H04BTransmission4%
H10BElectronic memory devices4%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h104%
PatentTitleYear
10,802,074Method and apparatus for analyzing phase noise in a signal from an electronic device20209,003,549'Analysis of an analog property of a signal'20158,891,602'Analyzing jitter with noise from the measurement environment'20148,473,233'Analyzing jitter in a clock timing signal'20137,388,440'Circuit and method to speed up PLL lock-time and prohibit frequency runaway'20086,977,400'Silicon germanium CMOS channel'20056,770,947'Laser-breakable fuse link with alignment and break point promotion structures'20046,566,730'Laser-breakable fuse link with alignment and break point promotion structures'20036,544,854'Silicon germanium CMOS channel'20036,455,363'System to improve ser immunity and punchthrough'20026,442,061'Single channel four transistor SRAM'20026,413,848'Self-aligned fuse structure and method with dual-thickness dielectric'20026,259,146'Self-aligned fuse structure and method with heat sink'20016,218,276'Silicide encapsulation of polysilicon gate and interconnect'20016,162,714'Method of forming thin polygates for sub quarter micron CMOS process'20006,090,651'Depletion free polysilicon gate electrodes'20006,061,264'Self-aligned fuse structure and method with anti-reflective coating'20006,037,233'Metal-encapsulated polysilicon gate and interconnect'20005,953,614'Process for forming self-aligned metal silicide contacts for MOS structure using single silicide-forming step'1999Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1999–2005Patents assigned to LSI LOGIC CORP (14)· patent assignee history
1999–2005Based in Cupertino, CA, US· patent location history
2008Patents assigned to CYPRESS SEMICONDUCTOR CORP (1)· patent assignee history
2008–2020Based in Santa Clara, CA, US· patent location history
2013–2015Patents assigned to GIUST GARY K (3)· patent assignee history
2020Patents assigned to JITTERLABS LLC (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| LSI LOGIC CORP | 14 | 1999–2005 |
| GIUST GARY Kself | 3 | 2013–2015 |
| CYPRESS SEMICONDUCTOR CORP | 1 | 2008 |
| JITTERLABS LLC | 1 | 2020 |
Locations
| Location | Patents | Span |
|---|---|---|
| Cupertino, California, US | 14 | 1999–2005 |
| Santa Clara, California, US | 5 | 2008–2020 |