Inventor
Ashok Pachamuthu
Inventor
Boise, ID, US
Overview
Patents· 6 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices33%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1033%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1033%
PatentTitleYear
11,037,910Semiconductor device having laterally offset stacked semiconductor dies202110,593,568Thrumold post package with reverse build up hybrid additive structure202010,586,780Semiconductor device modules including a die electrically connected to posts and related methods202010,325,874Device module having a plurality of dies electrically connected by posts201910,192,843Methods of making semiconductor device modules with increased yield201910,103,038Thrumold post package with reverse build up hybrid additive structure2018Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2018–2021Patents assigned to MICRON TECHNOLOGY INC (6)· patent assignee history
2018–2021Based in Boise, ID, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MICRON TECHNOLOGY INC | 6 | 2018–2021 |
Locations
| Location | Patents | Span |
|---|---|---|
| Boise, ID, US | 6 | 2018–2021 |