Inventor
Sergej Deutsch
Inventor
Hillsboro, OR, US
Overview
Patents· 25 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing36%
H04LTransmission of digital information, e.g. telegraphic communication24%
G01RMeasuring electric variables16%
G11CStatic stores8%
H03MCoding8%
H04WWireless communication networks6%
G09CCiphering or deciphering apparatus for cryptographic or other purposes involving the need for secrecy2%
PatentTitleYear
11,082,432Methods and apparatus to support reliable digital communications without integrity metadata202111,019,098Replay protection for memory based on key refresh202111,010,310Convolutional memory integrity202111,003,584Technology for managing memory tags202110,929,527Methods and arrangements for implicit integrity202110,855,815Security-oriented compression202010,845,416Software-based self-test and diagnosis using on-chip memory202010,802,910System for identifying and correcting data errors202010,788,532Software-based self-test and diagnosis using on-chip memory202010,769,272Technology to protect virtual machines from malicious virtual machine managers202010,761,928Combined secure mac and device correction using encrypted parity with multi-key domains202010,757,227Security-oriented compression202010,732,221Signal tracing using on-chip memory for in-system post-fabrication debug202010,594,491Cryptographic system memory management202010,585,809Convolutional memory integrity202010,498,865Security-oriented compression201910,444,279Non-invasive pre-bond TSV test using ring oscillators and multiple voltage levels201910,387,305Techniques for compression memory coloring201910,346,318Multi-stage memory integrity method and apparatus201910,261,854Memory integrity violation analysis method and apparatus20199,990,249Memory integrity with error detection and correction20189,864,007'Software-based self-test and diagnosis using on-chip memory'20189,720,036'Signal tracing using on-chip memory for in-system post-fabrication debug'20179,482,720'Non-invasive pre-bond TSV test using ring oscillators and multiple voltage levels'20168,914,689'Controlled toggle rate of non-test signals during modular scan testing of an integrated circuit'2014Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2014Patents assigned to CADENCE DESIGN SYSTEMS INC (1)· patent assignee history
2014Patents assigned to DEUTSCH SERGEJ (1)· patent assignee history
2014Patents assigned to IMEC (1)· patent assignee history
2014–2020Based in Durham, NC, US· patent location history
2016–2020Patents assigned to UNIV DUKE (7)· patent assignee history
2017–2020Based in Austin, TX, US· patent location history
2018–2021Patents assigned to INTEL CORP (17)· patent assignee history
2018–2021Based in Hillsboro, OR, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 17 | 2018–2021 |
| UNIV DUKE | 7 | 2016–2020 |
| CADENCE DESIGN SYSTEMS INC | 1 | 2014 |
| DEUTSCH SERGEJself | 1 | 2014 |
| IMEC | 1 | 2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hillsboro, OR, US | 17 | 2018–2021 |
| Durham, NC, US | 6 | 2014–2020 |
| Austin, Texas, US | 2 | 2017–2020 |