Inventor
ROBERT SANKMAN
Inventor
US
Overview
Patents· 22 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices38%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1038%
H05KPrinted circuits10%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h107%
H03KPulse technique3%
H01QAntennas, i.e. radio aerials2%
H10DInorganic electric semiconductor devices2%
PatentTitleYear
12,347,783Interconnect architecture with silicon interposer and EMIB202512,341,080Semiconductor device stack-up with bulk substrate material to mitigate hot spots202512,272,656Heterogeneous nested interposer package for IC chips202512,206,410Programmable logic device with fine-grained disaggregation202512,199,048Heterogeneous nested interposer package for IC chips202512,148,703EMIB patch on glass laminate substrate202412,003,023In-package 3D antenna202411,978,727Package on active silicon semiconductor packages202411,978,689Semiconductor device stack-up with bulk substrate material to mitigate hot spots202411,915,996Microelectronics assembly including top and bottom packages in stacked configuration with shared cooling202411,901,299Interconnect architecture with silicon interposer and EMIB202411,824,018Heterogeneous nested interposer package for IC chips202311,756,860Semiconductor device stack-up with bulk substrate material to mitigate hot spots202311,735,533Heterogeneous nested interposer package for IC chips202311,658,122EMIB patch on glass laminate substrate202311,652,020Thermal solutions for multi-package assemblies and methods for fabricating the same202311,652,057Disaggregated die interconnection with on-silicon cavity bridge202311,610,856Connectivity between integrated circuit dice in a multi-chip package202311,595,045Programmable logic device with fine-grained disaggregation202311,581,287Chip scale thin 3D die stacked package202311,557,541Interconnect architecture with silicon interposer and EMIB202311,515,232Liquid cooling through conductive interconnect2022Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2022–2025Patents assigned to INTEL CORP (22)· patent assignee history
2022–2025Based in US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 22 | 2022–2025 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 22 | 2022–2025 |