Inventor

Sundar Narayanan

Inventor

Cupertino, CA, US

Overview

31→

Patents

2003–2020

Patent span

Electricity

Primary field (CPC H)

Patents· 31 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H01Lprimary

H01LSemiconductor devices21%

H10NElectric solid-state devices not otherwise provided for21%

H10DInorganic electric semiconductor devices19%

H10BElectronic memory devices14%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1014%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h108%

G01NInvestigating or analysing materials by determining their chemical or physical properties3%

G11CStatic stores1%

PatentTitleYear

10,873,023Using aluminum as etch stop layer2020 10,749,110Memory stack liner comprising dielectric block layer material2020 10,693,062Regulating interface layer formation for two-terminal memory2020 10,522,754Liner layer for dielectric block layer2019 10,319,908Integrative resistive memory in backend metal layers2019 10,290,801Scalable silicon based resistive memory device2019 10,115,819Recessed high voltage metal oxide semiconductor transistor for RRAM cell2018 10,096,653Monolithically integrated resistive memory using integrated-circuit foundry compatible processes2018 10,062,845Flatness of memory cell surfaces2018 9,741,765'Monolithically integrated resistive memory using integrated-circuit foundry compatible processes'2017 9,697,874'Monolithic memory comprising 1T1R code memory and 1TnR storage class memory'2017 9,595,670'Resistive random access memory (RRAM) cell and method for forming the RRAM cell'2017 9,437,814'Mitigating damage from a chemical mechanical planarization process'2016 9,425,046'Method for surface roughness reduction after silicon germanium thin film deposition'2016 9,343,668'Low temperature in-situ doped silicon-based conductor material for memory cell'2016 9,209,396'Regulating interface layer growth with N2O for two-terminal memory'2015 8,445,381'Oxide-nitride stack gate dielectric'2013 7,371,637'Oxide-nitride stack gate dielectric'2008 7,351,663'Removing whisker defects'2008 7,189,652'Selective oxidation of gate stack'2007 7,172,914'Method of making uniform oxide layer'2007 7,094,707'Method of forming nitrided oxide in a hot wall single wafer furnace'2006 6,964,929'Method of forming a narrow gate, and product produced thereby'2005 6,943,126'Deuterium incorporated nitride'2005 6,905,893'Method and structure for determining a concentration profile of an impurity within a semiconductor layer'2005 6,803,330'Method for growing ultra thin nitrided oxide'2004 6,803,321'Nitride spacer formation'2004 6,794,269'Method for and structure formed from fabricating a relatively deep isolation structure'2004 6,774,012'Furnace system and method for selectively oxidizing a sidewall surface of a gate conductor by oxidizing a silicon sidewall in lieu of a refractory metal sidewall'2004 6,773,975'Formation of a shallow trench isolation structure in integrated circuits'2004 6,664,120'Method and structure for determining a concentration profile of an impurity within a semiconductor layer'2003

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2003–2013Patents assigned to CYPRESS SEMICONDUCTOR CORP (15)· patent assignee history

2003–2016Based in Santa Clara, CA, US· patent location history

2008–2013Based in Sunnyvale, CA, US· patent location history

2013Patents assigned to NARAYANAN SUNDAR (1)· patent assignee history

2013Patents assigned to RAMKUMAR KRISHNASWAMY (1)· patent assignee history

2015–2020Patents assigned to CROSSBAR INC (16)· patent assignee history

2015–2020Based in Cupertino, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
CROSSBAR INC	16	2015–2020
CYPRESS SEMICONDUCTOR CORP	15	2003–2013
NARAYANAN SUNDARself	1	2013
RAMKUMAR KRISHNASWAMY	1	2013

Locations

Location	Patents	Span
Cupertino, California, US	15	2015–2020
Santa Clara, California, US	14	2003–2016
Sunnyvale, California, US	2	2008–2013