Inventor

Mam-Tsung Wang

Inventor

Hsinchu, TW

Overview

1998–2003

Patent span

Electricity

Primary field (CPC H)

Patents· 29 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary

G11CStatic stores45%

H10BElectronic memory devices29%

H10DInorganic electric semiconductor devices24%

G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices3%

PatentTitleYear

6,614,687'Current source component with process tracking characteristics for compact programmed Vt distribution of flash EPROM'2003 6,525,361'Process and integrated circuit for a multilevel memory cell with an asymmetric drain'2003 6,455,898'Electrostatic discharge input protection for reducing input resistance'2002 6,432,782'8 bit per cell non-volatile semiconductor memory structure utilizing trench technology and dielectric floating gate'2002 6,397,377'Method of performing optical proximity corrections of a photo mask pattern by using a computer'2002 6,269,017'Multi level mask ROM with single current path'2001 6,259,140'Silicide blocking process to form non-silicided regions on MOS devices'2001 6,215,697'Multi-level memory cell device and method for self-converged programming'2001 6,204,529'8 bit per cell non-volatile semiconductor memory structure utilizing trench technology and dielectric floating gate'2001 6,181,604'Method for fast programming of EPROMS and multi-level flash EPROMS'2001 6,175,519'Virtual ground EPROM structure'2001 6,166,943'Method of forming a binary code of a ROM'2000 6,166,955'Apparatus and method for programming of flash EPROM memory'2000 6,140,682'Self protected stacked NMOS with non-silicided region to protect mixed-voltage I/O pad from ESD damage'2000 6,130,452'Virtual ground flash cell with asymmetrically placed source and drain and method of fabrication'2000 6,121,092'Silicide blocking process to form non-silicided regions on MOS devices'2000 6,055,190'Device and method for suppressing bit line column leakage during erase verification of a memory cell'2000 6,046,482'Cell structure for mask ROM'2000 6,040,993'Method for programming an analog/multi-level flash EEPROM'2000 6,031,766'Method and circuit for substrate current induced hot e-injection (SCIHE) approach for V.sub.T convergence at low V.sub.cc voltage'2000 6,028,790'Method and device for programming a non-volatile memory cell by controlling source current pulldown rate'2000 5,963,808'Method of forming an asymmetric bird\'s beak cell for a flash EEPROM'1999 5,959,892'Apparatus and method for programming virtual ground EPROM array cell without disturbing adjacent cells'1999 5,912,845'Method and circuit for substrate current induced hot e.sup.- injection (SCIHE) approach for V.sub.T convergence at low V.sub.CC voltage'1999 5,912,844'Method for flash EEPROM data writing'1999 5,895,241'Method for fabricating a cell structure for mask ROM'1999 5,893,738'Method for forming double density MROM array structure'1999 5,837,584'Virtual ground flash cell with asymmetrically placed source and drain and method of fabrication'1998 5,828,113'Double density MROM array structure'1998

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1998–2003Patents assigned to MACRONIX INT CO LTD (27)· patent assignee history

1998–2003Based in Hsinchu, TW· patent location history

1999–2000Based in Hsingchu, TW· patent location history

1999Based in Hsin Chu, TW· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
MACRONIX INT CO LTD	27	1998–2003

Locations

Location	Patents	Span
Hsinchu, TW	26	1998–2003
Hsingchu, TW	2	1999–2000
Hsin Chu, TW	1	1999