Inventor
Jiankang Bu
Inventor
Windham, ME, US
Overview
Patents· 25 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices36%
H10BElectronic memory devices23%
G11CStatic stores20%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h107%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests5%
G01RMeasuring electric variables2%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices2%
H01LSemiconductor devices2%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h102%
PatentTitleYear
9,972,681High voltage vertical semiconductor device with multiple pillars in a racetrack arrangement20188,502,296'Non-volatile memory cell with asymmetrical split gate and related system and method'20138,274,824'High-performance CMOS-compatible non-volatile memory cell and related method'20128,241,975'System and method for providing low voltage high density multi-bit storage flash memory'20128,198,708'System and method for improving CMOS compatible non volatile memory retention reliability'20128,114,738'System and method for providing low cost high endurance low voltage electrically erasable programmable read only memory'20128,097,923'Method for fabricating higher quality thicker gate oxide in a non-volatile memory cell and associated circuits'20128,013,400'Method and system for scaling channel length'20118,004,032'System and method for providing low voltage high density multi-bit storage flash memory'20117,910,420'System and method for improving CMOS compatible non volatile memory retention reliability'20117,855,146'Photo-focus modulation method for forming transistor gates and related transistor devices'20107,838,203'System and method for providing process compliant layout optimization using optical proximity correction to improve CMOS compatible non volatile memory retention reliability'20107,804,714'System and method for providing an EPROM with different gate oxide thicknesses'20107,790,491'Method for forming non-volatile memory cells and related apparatus and system'20107,781,289'Method for fabricating higher quality thicker gate oxide in a non-volatile memory cell and associated circuits'20107,777,271'System and method for providing low cost high endurance low voltage electrically erasable programmable read only memory'20107,773,423'Low power, CMOS compatible non-volatile memory cell and related method and memory array'20107,646,638'Non-volatile memory cell that inhibits over-erasure and related method and memory array'20107,586,792'System and method for providing drain avalanche hot carrier programming for non-volatile memory applications'20097,532,496'System and method for providing a low voltage low power EPROM based on gate oxide breakdown'20097,514,940'System and method for determining effective channel dimensions of metal oxide semiconductor devices'20097,512,499'System and method for determining substrate doping density in metal oxide semiconductor devices'20097,483,310'System and method for providing high endurance low cost CMOS compatible EEPROM devices'20097,471,572'System and method for enhancing erase performance in a CMOS compatible EEPROM device'20087,447,064'System and method for providing a CMOS compatible single poly EEPROM with an NMOS program transistor'2008Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2008–2013Patents assigned to NAT SEMICONDUCTOR CORP (24)· patent assignee history
2008–2013Based in Windham, ME, US· patent location history
2012–2013Patents assigned to BU JIANKANG (6)· patent assignee history
2012Patents assigned to PARKER DAVID COURTNEY (2)· patent assignee history
2012Patents assigned to BUDRI THANAS (1)· patent assignee history
2012Patents assigned to JACOBSON LEE JAMES (1)· patent assignee history
2018Based in Temecula, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| NAT SEMICONDUCTOR CORP | 24 | 2008–2013 |
| BU JIANKANGself | 6 | 2012–2013 |
| PARKER DAVID COURTNEY | 2 | 2012 |
| BUDRI THANAS | 1 | 2012 |
| JACOBSON LEE JAMES | 1 | 2012 |
Locations
| Location | Patents | Span |
|---|---|---|
| Windham, ME, US | 24 | 2008–2013 |
| Temecula, California, US | 1 | 2018 |