Inventor
Frederick Gruner
Inventor
Palo Alto, CA, US
Overview
Patents· 20 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H04Lprimary
H04LTransmission of digital information, e.g. telegraphic communication38%
G06FElectric digital data processing28%
H03KPulse technique9%
G11CStatic stores6%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests6%
G06TImage data processing or generation, in general3%
G09GArrangements or circuits for control of indicating devices using static means to present variable information3%
H04NPictorial communication, e.g. television3%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h103%
PatentTitleYear
9,294,085'High-voltage, low-inductance gas switch'20169,083,628'Content service aggregation system'20158,424,012'Context switching on a video processor having a scalar execution unit and a vector execution unit'20138,370,528'Content service aggregation system'20137,934,198'Prefix matching structure and method for fast packet switching'20117,765,328'Content service aggregation system'20107,562,196'Method and apparatus for determining precedence in a classification engine'20097,305,492'Content service aggregation system'20077,213,111'Method and apparatus for determining precedence in a classification engine'20077,174,441'Method and apparatus for providing internal table extensibility with external interface'20076,938,093'Bandwidth allocation for a data path'20056,920,542'Application processing employing a coprocessor'20056,898,673'Co-processor including a media access controller'20056,895,477'Ring-based memory requests in a shared memory multi-processor'20056,892,282'Ring based multi-processing system'20056,745,289'Processing packets in cache memory'20046,598,154'Precoding branch instructions to reduce branch-penalty in pipelined processors'20036,496,923'Length decode to detect one-byte prefixes and branch'20026,066,959'Logic array having multi-level logic planes'20005,977,794'Logic array having interleaved logic planes'1999Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1999–2003Patents assigned to INTEL CORP (4)· patent assignee history
1999–2015Based in Palo Alto, CA, US· patent location history
2004–2015Patents assigned to JUNIPER NETWORKS INC (10)· patent assignee history
2007Patents assigned to RAZA MICROELECTRONICS INC (2)· patent assignee history
2013–2016Patents assigned to GRUNER FREDERICK R (2)· patent assignee history
2013Patents assigned to BRYERS MARK (1)· patent assignee history
2016Based in Cedar Crest, NM, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| JUNIPER NETWORKS INC | 10 | 2004–2015 |
| INTEL CORP | 4 | 1999–2003 |
| GRUNER FREDERICK Rself | 2 | 2013–2016 |
| RAZA MICROELECTRONICS INC | 2 | 2007 |
| BRYERS MARK | 1 | 2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Palo Alto, California, US | 19 | 1999–2015 |
| Cedar Crest, NM, US | 1 | 2016 |