Inventor
Ashok Raj
Inventor
Portland, OR, US
Overview
Patents· 32 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing67%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use10%
H04LTransmission of digital information, e.g. telegraphic communication7%
G06QInformation and communication technology [ict] specially adapted for administrative, commercial, financial, managerial or supervisory purposes5%
G11CStatic stores5%
G06NComputing arrangements based on specific computational models2%
G08BSignalling systems, e.g. personal calling systems2%
H04MTelephonic communication2%
PatentTitleYear
11,048,512Apparatus and method to identify the source of an interrupt202111,025,544Network interface for data transport in heterogeneous computing environments202110,841,372Systems and methods for performing useful commissioned work using distributed networks202010,620,969System, apparatus and method for providing hardware feedback information in a processor202010,599,596Management of processor performance based on user interrupts202010,579,551Memory pressure notifier202010,474,596Providing dedicated resources for a system management mode of a processor201910,430,267Determine when an error log was created201910,387,072Systems and method for dynamic address based mirroring201910,324,852System and method to increase availability in a multi-level memory configuration201910,319,458Hardware apparatuses and methods to check data storage devices for transient faults201910,318,368Enabling error status and reporting in a machine check architecture201910,296,416Read from memory instructions, processors, methods, and systems, that do not take exception on defective data201910,223,187Instruction and logic to expose error domain topology to facilitate failure isolation in a processor201910,185,619Handling of error prone cache line slots of memory side cache of multi-level system memory201910,162,761Apparatus and method for system physical address to memory module address translation201810,157,142Offload data transfer engine for a block data transfer interface20189,904,586'Interfacing with block-based storage in a processor'20189,864,603'Instruction and logic for machine check interrupt management'20189,842,015'Instruction and logic for machine checking communication'20179,652,747'Context based alert system'20179,595,349'Hardware apparatuses and methods to check data storage devices for transient faults'20179,396,059'Exchange error information from platform firmware to operating system'20169,389,942'Determine when an error log was created'20169,384,076'Allocating machine check architecture banks'20169,141,454'Signaling software recoverable errors'20158,671,309'Mechanism for advanced server machine check recovery and associated system software enhancements'20147,636,832'I/O translation lookaside buffer performance'20097,447,820'Retargeting of platform interrupts'20087,194,540'Mechanism for allowing multiple entities on the same host to handle messages of same service class in a cluster'20077,039,922'Cluster with multiple paths between hosts and I/O controllers'20066,772,320'Method and computer program for data conversion in a heterogeneous communications network'2004Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2004–2021Patents assigned to INTEL CORP (31)· patent assignee history
2004–2021Based in Portland, OR, US· patent location history
2014Patents assigned to KUMAR MOHAN J (1)· patent assignee history
2014Patents assigned to RAJ ASHOK (1)· patent assignee history
2014Patents assigned to RANGANATHAN NARAYAN (1)· patent assignee history
2020Patents assigned to HOOT LIVE INC (1)· patent assignee history
2020Based in San Francisco, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 31 | 2004–2021 |
| HOOT LIVE INC | 1 | 2020 |
| KUMAR MOHAN J | 1 | 2014 |
| RAJ ASHOKself | 1 | 2014 |
| RANGANATHAN NARAYAN | 1 | 2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Portland, OR, US | 31 | 2004–2021 |
| San Francisco, California, US | 1 | 2020 |