LexDanaLexDanabeta
Inventor

Brian S. Leibowitz

Inventor
San Francisco, CA, US

Overview

128→
Patents
2009–2021
Patent span
Electricity
Primary field (CPC H)

Patents· 128 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H04Lprimary
H04LTransmission of digital information, e.g. telegraphic communication24%
G06FElectric digital data processing12%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses10%
H03KPulse technique10%
G11CStatic stores8%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use5%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h104%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications3%
G01RMeasuring electric variables2%
H01JElectric discharge tubes or discharge lamps2%
PatentTitleYear
11,115,247Methods and circuits for asymmetric distribution of channel equalization between devices202111,063,791Receiver with clock recovery circuit and adaptive sample and equalizer timing202111,023,403Chip to chip interface with scalable bandwidth202111,022,639Integrated circuit that injects offsets into recovered clock to simulate presence of jitter in input signal202110,951,218Multi-mode clock multiplier202110,938,605High-speed signaling systems and methods with adaptable, continuous-time equalization202110,924,124Downshift techniques for oscillator with feedback loop202110,887,076Receiver with enhanced clock and data recovery202110,880,128Decision feedback equalizer202010,855,496Edge based partial response equalization202010,840,920Method and apparatus for source-synchronous signaling202010,770,124Memory device comprising programmable command-and-address and/or data interfaces202010,764,093DFE margin test methods and circuits that decouple sample feedback timing202010,756,849Self referenced single-ended chip to chip communication202010,700,671Data transmission using delayed timing signals202010,686,632Methods and circuits for asymmetric distribution of channel equalization between devices202010,650,872Memory component with multiple command/address sampling modes202010,630,300Downshift techniques for oscillator with feedback loop202010,608,652Frequency-agile clock multiplier202010,581,440Detecting power supply noise events and initiating corrective action202010,560,291High-speed signaling systems and methods with adaptable, continuous-time equalization202010,541,693Method and apparatus for source-synchronous signaling202010,536,304Receiver with clock recovery circuit and adaptive sample and equalizer timing202010,521,391Chip to chip interface with scalable bandwidth201910,466,289Apparatus and method for controllably injecting jitter into recovered clock to simulate presence of jitter in input signal201910,452,601Interface with variable data rate201910,432,389Receiver with enhanced clock and data recovery201910,404,258Integrated circuit device having an injection-locked oscillator201910,401,900Using a stuttered clock signal to reduce self-induced voltage noise201910,404,236Receiver with time-varying threshold voltage201910,397,028Decision feedback equalizer201910,263,761Clock and data recovery having shared clock generator201910,230,379Downshift techniques for oscillator with feedback loop201910,211,841Method and apparatus for source-synchronous signaling201910,205,461Integrated circuit having a clock deskew circuit that includes an injection-locked oscillator201910,205,614High-speed signaling systems with adaptable pre-emphasis and equalization201910,205,458Run-time output clock determination201910,192,598Memory device comprising programmable command-and-address and/or data interfaces201910,170,170Memory control component with dynamic command/address signaling rate201910,135,646High-speed signaling systems and methods with adaptable, continuous-time equalization201810,135,647Methods and circuits for asymmetric distribution of channel equalization between devices201810,135,427Receiver with time-varying threshold voltage201810,067,519On-chip regulator with variable load compensation201810,050,771Clock and data recovery having shared clock generator201810,044,530Edge based partial response equalization201810,003,484High-speed signaling systems with adaptable pre-emphasis and equalization20189,973,328Receiver with enhanced clock and data recovery20189,940,299Interface with variable data rate20189,900,189'Methods and circuits for asymmetric distribution of channel equalization between devices'20189,860,089'High-speed signaling systems and methods with adaptable, continuous-time equalization'20189,859,899'Integrated circuit device having an injection-locked oscillator'20189,843,315'Data transmission using delayed timing signals'20179,843,309'Receiver with time-varying threshold voltage'20179,818,463'Memory control component with inter-rank skew tolerance'20179,806,727'Integrated circuit having a clock deskew circuit that includes an injection-locked oscillator'20179,785,500'Reduced-overhead error detection and correction'20179,774,441'Clock and data recovery using receiver clock spread spectrum modulation and offset compensation'20179,768,947'Clock and data recovery having shared clock generator'20179,748,960'Method and apparatus for source-synchronous signaling'20179,742,602'High-speed signaling systems with adaptable pre-emphasis and equalization'20179,735,791'Jitter-based clock selection'20179,734,357'Process authenticated memory page encryption'20179,734,879'Memory device comprising programmable command-and-address and/or data interfaces'20179,720,033'On-chip parameter measurement'20179,684,321'On-chip regulator with variable load compensation'20179,660,844'Decision feedback equalizer'20179,577,816'Clock and data recovery having shared clock generator'20179,569,308'Reduced-overhead error detection and correction'20179,569,396'Interface with variable data rate'20179,563,597'High capacity memory systems with inter-rank skew tolerance'20179,564,912'Integrated circuit having a clock deskew circuit that includes an injection-locked oscillator'20179,565,036'Techniques for adjusting clock signals to compensate for noise'20179,553,745'High-speed signaling systems with adaptable pre-emphasis and equalization'20179,465,961'Methods and circuits for securing proprietary memory transactions'20169,455,825'Receiver with clock recovery circuit and adaptive sample and equalizer timing'20169,453,879'On-die system for monitoring and predicting performance'20169,425,997'Methods and circuits for asymmetric distribution of channel equalization between devices'20169,423,441'Integrated circuit having receiver jitter tolerance (“JTOL”) measurement'20169,419,781'Receiver with enhanced clock and data recovery'20169,419,663'High-speed signaling systems and methods with adaptable, continuous-time equalization'20169,391,816'Edge based partial response equalization'20169,344,074'Low-latency, frequency-agile clock multiplier'20169,337,992'Clock and data recovery using receiver clock spread spectrum modulation and offset compensation'20169,304,579'Fast-wake memory control'20169,287,880'Integrated circuit device having an injection-locked oscillator'20169,264,055'Integrated circuit having a clock deskew circuit that includes an injection-locked oscillator'20169,262,342'Process authenticated memory page encryption'20169,215,112'Decision feedback equalizer'20159,178,688'Receiver with clock recovery circuit and adaptive sample and equalizer timing'20159,178,647'Interface with variable data rate'20159,148,322'High-speed signaling systems with adaptable pre-emphasis and equalization'20159,137,063'High-speed signaling systems with adaptable pre-emphasis and equalization'20159,117,496'Memory device comprising programmable command-and-address and/or data interfaces'20159,110,596'Fast-wake memory'20159,094,238'High-speed signaling systems with adaptable pre-emphasis and equalization'20159,083,280'Techniques for phase detection'20159,077,575'Methods and circuits for asymmetric distribution of channel equalization between devices'20159,046,909'On-chip regulator with variable load compensation'20158,989,249'High-speed signaling systems with adaptable pre-emphasis and equalization'20158,964,879'Crosstalk reduction coding schemes'20158,943,224'Chip selection in a symmetric interconnection topology'20158,941,420'Low-latency, frequency-agile clock multiplier'20158,934,525'High-speed signaling systems and methods with adaptable, continuous-time equalization'20158,929,496'Receiver with enhanced clock and data recovery'20158,923,467'Clock and data recovery using receiver clock spread spectrum modulation and offset compensation'20148,855,217'Interface with variable data rate'20148,836,394'Method and apparatus for source-synchronous signaling'20148,824,222'Fast-wake memory'20148,824,224'Frequency-agile strobe window generation'20148,811,553'Edge based partial response equalization'20148,804,397'Integrated circuit having a clock deskew circuit that includes an injection-locked oscillator'20148,766,647'Method and apparatus for power sequence timing to mitigate supply resonance in power distribution network'20148,743,973'Receiver resistor network for common-mode signaling'20148,667,347'Active calibration for high-speed memory devices'20148,618,869'Fast power-on bias circuit'20138,588,280'Asymmetric communication on shared links'20138,548,110'Receiver with clock recovery circuit and adaptive sample and equalizer timing'20138,477,835'Methods and circuits for asymmetric distribution of channel equalization between devices'20138,477,834'Partial response decision-feedback equalization with adaptation based on edge samples'20138,422,590'Apparatus and methods for differential signal receiving'20138,311,176'Clock and data recovery employing piece-wise estimation on the derivative of the frequency'20128,289,032'Integrated circuit having receiver jitter tolerance (“JTOL”) measurement'20128,279,948'Interface with variable data rate'20128,279,976'Signaling with superimposed differential-mode and common-mode signals'20128,198,930'Reducing power-supply-induced jitter in a clock-distribution circuit'20128,159,274'Signaling with superimposed clock and data signals'20127,949,041'Methods and circuits for asymmetric distribution of channel equalization between devices'20117,590,175'DFE margin test methods and circuits that decouple sample and feedback timing'2009

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2009–2021Patents assigned to RAMBUS INC (119)· patent assignee history
2009–2021Based in San Francisco, CA, US· patent location history
2012–2019Patents assigned to LEIBOWITZ BRIAN S (25)· patent assignee history
2012–2019Patents assigned to ZERBE JARED L (15)· patent assignee history
2012–2016Patents assigned to LEE HAE-CHANG (11)· patent assignee history
2012–2017Patents assigned to LEIBOWITZ BRIAN (11)· patent assignee history
2016Based in Sunnyvale, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
RAMBUS INC1192009–2021
LEIBOWITZ BRIAN Sself252012–2019
ZERBE JARED L152012–2019
LEE HAE-CHANG112012–2016
LEIBOWITZ BRIANself112012–2017
Locations
LocationPatentsSpan
San Francisco, California, US1272009–2021
Sunnyvale, California, US12016