LexDanaLexDanabeta
Inventor

Kazufumi Komura

Inventor
Kasugai, JP

Overview

18→
Patents
2002–2014
Patent span
Physics
Primary field (CPC G)

Patents· 18 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary
G11CStatic stores54%
G01RMeasuring electric variables8%
G06FElectric digital data processing8%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h108%
H03KPulse technique4%
H10BElectronic memory devices4%
H10DInorganic electric semiconductor devices4%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use4%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests4%
PatentTitleYear
8,742,786'Semiconductor device and operation monitoring method for semiconductor device'20148,023,353'Semiconductor memory device, refresh control method thereof, and test method thereof'20117,872,293'Capacitance cell, semiconductor device, and capacitance cell arranging method'20117,764,559'Semiconductor memory device, refresh control method thereof, and test method thereof'20107,663,175'Semiconductor integrated circuit device'20107,650,553'Semiconductor integrated circuit apparatus and interface test method'20107,495,990'Semiconductor memory device and method of controlling the semiconductor memory device'20097,463,076'Power consumption reduction circuit for clock network'20087,301,833'Shift redundancy circuit, method for controlling shift redundancy circuit, and semiconductor memory device'20077,245,549'Semiconductor memory device and method of controlling the semiconductor memory device'20077,206,246'Semiconductor memory device, refresh control method thereof, and test method thereof'20077,135,895'Semiconductor device having output circuit adaptively suppressing SSO noise'20066,999,360'Shift redundancy circuit, method for controlling shift redundancy circuit, and semiconductor memory device'20066,956,777'Semiconductor memory device and control method thereof'20056,879,200'Delay circuit, semiconductor integrated circuit device containing a delay circuit and delay method'20056,845,051'Semiconductor memory device and data access method for semiconductor memory device'20056,795,328'Semiconductor memory device'20046,490,215'Semiconductor memory device and refreshing method of semiconductor memory device'2002

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2002–2008Patents assigned to FUJITSU LTD (11)· patent assignee history
2002–2014Based in Kasugai, JP· patent location history
2009–2010Patents assigned to FUJITSU MICROELECTRONICS LTD (3)· patent assignee history
2010–2014Patents assigned to FUJITSU SEMICONDUCTOR LTD (4)· patent assignee history
2014Patents assigned to ASANO SHIGETAKA (1)· patent assignee history
2014Patents assigned to FUJIMURA KEIICHI (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
FUJITSU LTD112002–2008
FUJITSU SEMICONDUCTOR LTD42010–2014
FUJITSU MICROELECTRONICS LTD32009–2010
ASANO SHIGETAKA12014
FUJIMURA KEIICHI12014
Locations
LocationPatentsSpan
Kasugai, JP182002–2014