Inventor
Peter J. McElheny
Inventor
Morgan Hill, CA, US
Overview
Patents· 41 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices24%
H10BElectronic memory devices13%
G11CStatic stores12%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1012%
H03KPulse technique10%
G06FElectric digital data processing9%
H01LSemiconductor devices6%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests6%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices3%
H04LTransmission of digital information, e.g. telegraphic communication3%
PatentTitleYear
10,778,414Active interposer for localized programmable integrated circuit reconfiguration202010,291,397Active interposer for localized programmable integrated circuit reconfiguration20199,634,094'Strain-enhanced transistors with adjustable layouts'20179,576,617'Multiport memory element circuitry'20179,484,411'Integrated circuit and a method to optimize strain inducing composites'20168,995,177'Integrated circuits with asymmetric transistors'20158,765,541'Integrated circuit and a method to optimize strain inducing composites'20148,755,218'Multiport memory element circuitry'20148,664,725'Strain enhanced transistors with adjustable layouts'20148,638,594'Integrated circuits with asymmetric transistors'20148,627,264'Automated verification of transformational operations on a photomask representation'20148,492,798'Electrical fuse with sacrificial contact'20138,138,786'Apparatus and methods for adjusting performance of integrated circuits'20128,130,538'Non-volatile memory circuit including voltage divider with phase change memory devices'20128,057,964'Photolithographic reticles with electrostatic discharge protection structures'20117,902,611'Integrated circuit well isolation structures'20117,812,408'Integrated circuits with metal-oxide-semiconductor transistors having enhanced gate depletion layers'20107,759,226'Electrical fuse with sacrificial contact'20107,741,716'Integrated circuit bond pad structures'20107,639,033'On-chip voltage regulator using feedback on process/product parameters'20097,573,317'Apparatus and methods for adjusting performance of integrated circuits'20097,514,758'Dual-oxide transistors for the improvement of reliability and off-state leakage'20097,348,827'Apparatus and methods for adjusting performance of programmable logic devices'20087,277,346'Method and system for hard failure repairs in the field'20077,235,884'Local control of electrical and mechanical properties of copper interconnects to achieve stable and reliable via'20077,170,308'On-chip voltage regulator using feedback on process/product parameters'20077,129,745'Apparatus and methods for adjusting performance of integrated circuits'20067,125,760'Method for implementing electro-static discharge protection in silicon-on-insulator devices'20067,107,566'Programmable logic device design tools with gate leakage reduction capabilities'20067,045,427'Polysilicon gate doping level variation for reduced leakage current'20066,951,792'Dual-oxide transistors for the improvement of reliability and off-state leakage'20056,906,387'Method for implementing electro-static discharge protection in silicon-on-insulator devices'20056,829,127'High performance capacitor structure'20046,750,106'Polysilicon gate doping level variation for reduced leakage current'20046,740,944'Dual-oxide transistors for the improvement of reliability and off-state leakage'20046,624,467'EEPROM active area castling'20036,472,272'Castled active area mask'20026,265,746'Highly resistive interconnects'20016,187,634'Process for making an EEPROM active area castling'20016,127,217'Method of forming highly resistive interconnects'20006,038,171'Field emission erasable programmable read-only memory'2000Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2000–2017Patents assigned to ALTERA CORP (39)· patent assignee history
2000–2020Based in Morgan Hill, CA, US· patent location history
2011–2014Patents assigned to MCELHENY PETER J (7)· patent assignee history
2011–2014Patents assigned to HSU CHE TA (3)· patent assignee history
2013–2014Patents assigned to LEE SHIH-LIN S (3)· patent assignee history
2014Patents assigned to VENKITACHALAM GIRISH (3)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ALTERA CORP | 39 | 2000–2017 |
| MCELHENY PETER Jself | 7 | 2011–2014 |
| HSU CHE TA | 3 | 2011–2014 |
| LEE SHIH-LIN S | 3 | 2013–2014 |
| VENKITACHALAM GIRISH | 3 | 2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Morgan Hill, California, US | 41 | 2000–2020 |