Inventor
Hayden C. Cranford, Jr.
Inventor
Cary, NC, US
Overview
Patents· 109 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H04Lprimary
H04LTransmission of digital information, e.g. telegraphic communication23%
H03KPulse technique13%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses12%
G01RMeasuring electric variables9%
H04BTransmission7%
G06FElectric digital data processing7%
H03FAmplifiers6%
G05FSystems for regulating electric or magnetic variables5%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h103%
H03MCoding2%
PatentTitleYear
10,396,811Temperature compensation for reference voltages in an analog-to-digital converter20199,281,810'Current mode logic circuit with multiple frequency modes'20169,231,796'Power aware equalization in a serial communications link'20168,989,313'Adaptable receiver detection'20158,798,204'Serial link receiver for handling high speed transmissions'20148,793,365'Environmental and computing cost reduction with improved reliability in workload assignment to distributed computing nodes'20148,363,736'Test circuit for serial link receiver'20138,183,920'Variable gain amplifier with reduced power consumption'20128,130,887'Method and arrangements for link power reduction'20128,077,534'Adaptive noise suppression using a noise look-up table'20118,054,867'Apparatus for transmitting data and additional information simultaneously within a wire-based communication system'20118,054,926'Clock and data recovery system and method for clock and data recovery based on a forward error correction'20118,051,340'System and method for balancing delay of signal communication paths through well voltage adjustment'20118,016,482'Method and systems of powering on integrated circuit'20117,995,660'Receiver termination circuit for a high speed direct current (DC) serial link'20117,940,846'Test circuit for serial link receiver'20117,936,208'Bias circuit for a MOS device'20117,932,774'Structure for intrinsic RC power distribution for noise filtering of analog supplies'20117,898,286'Critical path redundant logic for mitigation of hardware across chip variation'20117,893,766'Adaptive common mode bias for differential amplifier input circuits'20117,840,916'Structure for on-chip electromigration monitoring system'20107,809,054'One-sample-per-bit decision feedback equalizer (DFE) clock and data recovery'20107,770,139'Design structure for a flexible multimode logic element for use in a configurable mixed-logic signal distribution path'20107,769,057'High speed serial link output stage having self adaptation for various impairments'20107,755,420'Intrinsic RC power distribution for noise filtering of analog supplies'20107,719,302'On-chip electromigration monitoring'20107,716,007'Design structures of powering on integrated circuit'20107,698,802'Method for manufacturing a calibration device'20107,692,447'Driver circuit'20107,684,517'Reducing power consumption in signal detection'20107,671,678'Serial link output stage differential amplifier and method'20107,661,052'Using statistical signatures for testing high-speed circuits'20107,646,839'Unified digital architecture'20107,624,289'Power network reconfiguration using MEM switches'20097,570,071'Impedance calibration for source series terminated serial link transmitter'20097,567,614'Altering power consumption in communication links based on measured noise'20097,539,473'Overshoot reduction in VCO calibration for serial link phase lock loop (PLL)'20097,522,000'Design structure for a serial link output stage differential amplifier'20097,522,687'Clock and data recovery system and method for clock and data recovery based on a forward error correction'20097,512,177'Method and apparatus for generating random jitter'20097,511,548'Clock distribution network, structure, and method for providing balanced loading in integrated circuit clock trees'20097,511,530'Nodal charge compensation for SST driver having data mux in output stage'20097,501,880'Body-biased enhanced precision current mirror'20097,486,127'Transistor switch with integral body connection to prevent latchup'20097,483,806'Design structures, method and systems of powering on integrated circuit'20097,479,819'Clock distribution network, structure, and method for providing balanced loading in integrated circuit clock trees'20097,477,713'method for providing automatic adaptation to frequency offsets in high speed serial links'20097,471,101'Systems and methods for controlling of electro-migration'20087,460,602'Method for performing high speed serial link output stage having self adaptation for various impairments'20087,449,942'Intrinsic RC power distribution for noise filtering of analog supplies'20087,429,877'Design structure for a flexible multimode logic element for use in a configurable mixed-logic signal distribution path'20087,418,069'Clock data recovering system with external early/late input'20087,418,032'Altering power consumption in communication links based on measured noise'20087,411,422'Driver/equalizer with compensation for equalization non-idealities'20087,408,374'Systems and methods for controlling of electro-migration'20087,406,135'Reducing power consumption in signal detection'20087,405,620'Differential amplifier and method'20087,403,039'Flexible multimode logic element for use in a configurable mixed-logic signal distribution path'20087,404,114'System and method for balancing delay of signal communication paths through well voltage adjustment'20087,397,876'Methods and arrangements for link power reduction'20087,394,273'On-chip electromigration monitoring system'20087,391,266'Serial link output stage differential amplifier and method'20087,391,271'Adjustment of PLL bandwidth for jitter control using feedback circuitry'20087,368,902'Impedance calibration for source series terminated serial link transmitter'20087,362,138'Flexible multimode logic element for use in a configurable mixed-logic signal distribution path'20087,349,498'Method and system for data and edge detection with correlation tables'20087,346,094'System and method for transmitting data and additional information simultaneously within a wire based communication system'20087,340,660'Method and system for using statistical signatures for testing high-speed circuits'20087,339,390'Systems and methods for controlling of electro-migration'20087,332,932'Serial link receiver with wide input voltage range and tolerance to high power voltage supply'20087,317,777'Digital adaptive control loop for data deserialization'20087,315,594'Clock data recovering system with external early/late input'20087,307,447'Self series terminated serial link transmitter having segmentation for amplitude, pre-emphasis, and slew rate control and voltage regulation for amplitude accuracy and high voltage protection'20077,305,571'Power network reconfiguration using MEM switches'20077,295,604'Method for determining jitter of a signal in a serial link and high speed serial link'20077,289,572'Method and system for scalable pre-driver to driver interface'20077,286,620'Equalizer for reduced intersymbol interference via partial clock switching'20077,279,950'Method and system for high frequency clock signal gating'20077,268,632'Structure and method for providing gate leakage isolation locally within analog circuits'20077,268,613'Transistor switch with integral body connection to prevent latchup'20077,218,135'Method and apparatus for reducing noise in a dynamic manner'20077,187,206'Power savings in serial link transmitters'20077,149,269'Receiver for clock and data recovery and method for calibrating sampling phases in a receiver for clock and data recovery'20067,142,624'Analog unidirectional serial link architecture'20067,088,766'Dynamic measurement of communication channel characteristics using direct sequence spread spectrum (DSSS) systems, methods and program products'20067,082,484'Architecture for advanced serial link between two cards'20067,081,842'Electronic component value trimming systems'20067,053,712'Method and apparatus for controlling common-mode output voltage in fully differential amplifiers'20067,042,277'Circuit and method for reducing jitter in a PLL of high speed serial links'20067,034,566'Method and circuit for increased noise immunity for clocking signals in high speed digital systems'20066,999,544'Apparatus and method for oversampling with evenly spaced samples'20066,993,107'Analog unidirectional serial link architecture'20066,977,558'Self-adaptive voltage regulator for a phase-locked loop'20056,970,529'Unified digital architecture'20056,968,413'Method and system for configuring terminators in a serial communication system'20056,717,997'Apparatus and method for current demand distribution in electronic systems'20046,332,166'Adaptive interface apparatus and method for data terminal elements in a communication network transmitting and receiving ethernet over a shielded twisted pair cabling system'20016,298,458'System and method for manufacturing test of a physical layer transceiver'20016,275,094'CMOS device and circuit and method of operation dynamically controlling threshold voltage'20016,087,861'Data network drivers including balanced current supplies and related methods'20006,031,394'Low voltage CMOS circuit for on/off chip drive at high voltage'20005,942,999'Controllable integrated linear attenuator for a D/A converter'19995,872,446'Low voltage CMOS analog multiplier with extended input dynamic range'19994,752,699'On chip multiple voltage generation using a charge pump and plural feedback sense circuits'19884,638,464'Charge pump system for non-volatile ram'19874,536,720'Programmable oscillator with power down feature and frequency adjustment'19854,429,237'High voltage on chip FET driver'19844,404,577'Electrically alterable read only memory cell'19834,004,164'Compensating current source'1977Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1977–2016Patents assigned to IBM (107)· patent assignee history
1977Based in Durham, NC, US· patent location history
1983–2010Based in Apex, NC, US· patent location history
2005–2019Based in Cary, NC, US· patent location history
2011–2014Patents assigned to CRANFORD JR HAYDEN C (4)· patent assignee history
2011–2014Patents assigned to ARSOVSKI IGOR (2)· patent assignee history
2012–2014Patents assigned to CHEN MINHAN (2)· patent assignee history
2016–2019Patents assigned to GLOBALFOUNDRIES INC (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 107 | 1977–2016 |
| CRANFORD JR HAYDEN Cself | 4 | 2011–2014 |
| ARSOVSKI IGOR | 2 | 2011–2014 |
| CHEN MINHAN | 2 | 2012–2014 |
| GLOBALFOUNDRIES INC | 2 | 2016–2019 |
Locations
| Location | Patents | Span |
|---|---|---|
| Cary, NC, US | 83 | 2005–2019 |
| Apex, NC, US | 25 | 1983–2010 |
| Durham, NC, US | 1 | 1977 |