Inventor
Robert E. Frickey
Inventor
Sacramento, CA, US
Overview
Patents· 13 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing65%
G11CStatic stores35%
PatentTitleYear
10,303,571Data recovery in memory devices201910,236,069Word line read disturb error reduction through fine grained access counter mechanism201910,067,829Managing redundancy information in a non-volatile memory201810,025,535Measurement and reporting of the latency of input and output operations by a solid state drive to a host20189,817,600'Configuration information backup in memory systems'20179,679,658'Method and apparatus for reducing read latency for a block erasable non-volatile memory'20179,552,159'Configuration information backup in memory systems'20179,543,019'Error corrected pre-read for upper page write in a multi-level cell memory'20179,524,774'Lower page read for multi-level cell memory'20169,354,973'Data integrity management in memory systems'20169,236,136'Lower page read for multi-level cell memory'20169,183,091'Configuration information backup in memory systems'20158,332,578'Method and system to improve the performance of a multi-level cell (MLC) NAND flash memory'2012Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2012–2019Patents assigned to INTEL CORP (13)· patent assignee history
2012Patents assigned to FRICKEY III ROBERT E (1)· patent assignee history
2012Patents assigned to HUGHES JONATHAN M (1)· patent assignee history
2012–2019Based in Sacramento, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 13 | 2012–2019 |
| FRICKEY III ROBERT Eself | 1 | 2012 |
| HUGHES JONATHAN M | 1 | 2012 |
Locations
| Location | Patents | Span |
|---|---|---|
| Sacramento, California, US | 13 | 2012–2019 |