Inventor

Joseph I. Chamdani

Inventor

Santa Clara, CA, US

Overview

2000–2021

Patent span

Physics

Primary field (CPC G)

Patents· 59 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing55%

H04LTransmission of digital information, e.g. telegraphic communication17%

G06TImage data processing or generation, in general6%

G09BEducational or demonstration appliances5%

G16HHealthcare informatics, i.e. information and communication technology [ict] specially adapted for the handling or processing of medical or healthcare data5%

H03MCoding5%

H04QSelecting4%

A63FCard, board, or roulette games1%

H03KPulse technique1%

PatentTitleYear

10,950,025Low-latency body area network for capturing body motions2021 10,803,066Methods and systems for hardware acceleration of database operations and queries for a versioned database based on multiple hardware accelerators2020 10,755,466Method and apparatus for comparing two motions2020 10,672,173System and method for capturing and analyzing motions to be shared2020 10,361,903Federated management of intelligent service modules2019 10,304,230System and method for capturing and analyzing motions to render a human avatar animation2019 10,157,488System and method for capturing and analyzing motions2018 9,661,085'Federated management of intelligent service modules'2017 9,542,442'Accessing data in a column store database based on hardware compatible indexing and replicated reordered columns'2017 9,424,315'Methods and systems for run-time scheduling database operations that are executed in hardware'2016 9,378,231'Accessing data in column store database based on hardware compatible data structures'2016 9,143,841'Federated management of intelligent service modules'2015 9,141,670'Methods and systems for hardware acceleration of streamed database operations and queries based on multiple hardware accelerators'2015 8,862,625'Accessing data in a column store database based on hardware compatible indexing and replicated reordered columns'2014 8,468,151'Methods and systems for hardware acceleration of database operations and queries based on multiple hardware accelerators'2013 8,458,129'Methods and systems for real-time continuous updates'2013 8,244,718'Methods and systems for hardware acceleration of database operations and queries'2012 8,234,267'Hardware accelerated reconfigurable processor for accelerating database operations and queries'2012 8,229,918'Hardware accelerated reconfigurable processor for accelerating database operations and queries'2012 8,224,800'Hardware accelerated reconfigurable processor for accelerating database operations and queries'2012 8,165,988'Fast batch loading and incremental loading of data into a database'2012 7,966,343'Accessing data in a column store database based on hardware compatible data structures'2011 7,952,997'Congestion management groups'2011 7,908,259'Hardware accelerated reconfigurable processor for accelerating database operations and queries'2011 7,895,151'Fast bulk loading and incremental loading of data into a database'2011 7,587,581'Multiple-thread processor with in-pipeline, thread selectable storage'2009 7,539,929'Error correction for data communication'2009 7,460,528'Processing data packets at a storage service module of a switch'2008 7,433,351'Isolation of data, control, and management traffic in a storage area network'2008 7,382,776'Performing block storage virtualization at a switch'2008 7,316,021'Switching method in a multi-threaded processor'2008 7,194,550'Providing a single hop communication path between a storage device and a network switch'2007 7,185,338'Processor with speculative multithreading and hardware to support multithreading software'2007 7,185,185'Multiple-thread processor with in-pipeline, thread selectable storage'2007 7,133,416'Converting data signals in a multiple communication protocol system area network'2006 7,120,915'Thread switch circuit design and signal encoding for vertical threading'2006 7,110,394'Packet switching apparatus including cascade ports and method for switching packets'2006 7,088,735'Processing data packets in a multiple protocol system area network'2006 6,985,975'Packet lockstep system and method'2006 6,968,491'Generating a check matrix for error correction'2005 6,938,147'Processor with multiple-thread, vertically-threaded pipeline'2005 6,920,601'Error correction for data communication'2005 6,920,588'Transmitting data in a communication network'2005 6,801,997'Multiple-thread processor with single-thread interface shared among threads'2004 6,694,347'Switching method in a multi-threaded processor'2004 6,678,796'System and method for scheduling memory instructions to provide adequate prefetch latency'2004 6,542,991'Multiple-thread processor with single-thread interface shared among threads'2003 6,507,862'Switching method in a multi-threaded processor'2003 6,490,658'Data prefetch technique using prefetch cache, micro-TLB, and history file'2002 6,487,715'Dynamic code motion optimization and path tracing'2002 6,433,603'Pulse-based high speed flop circuit'2002 6,420,903'High speed multiple-bit flip-flop'2002 6,351,808'Vertically and horizontally threaded processor with multidimensional storage for storing thread data'2002 6,341,347'Thread switch logic in a multiple-thread processor'2002 6,311,261'Apparatus and method for improving superscalar processors'2001 6,175,898'Method for prefetching data using a micro-TLB'2001 6,112,019'Distributed instruction queue'2000 6,058,466'System for allocation of execution resources amongst multiple executing processes'2000 6,035,374'Method of executing coded instructions in a multiprocessor having shared execution resources including active, nap, and sleep states in accordance with cache miss latency'2000

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2000–2009Patents assigned to SUN MICROSYSTEMS INC (20)· patent assignee history

2000–2021Based in Santa Clara, CA, US· patent location history

2000–2001Based in Marietta, GA, US· patent location history

2005–2007Patents assigned to SANERA SYSTEMS INC (7)· patent assignee history

2011–2020Patents assigned to TERADATA US INC (16)· patent assignee history

2012–2016Patents assigned to CHAMDANI JOSEPH I (10)· patent assignee history

2012–2016Patents assigned to BRANSCOME JEREMY (9)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
SUN MICROSYSTEMS INC	20	2000–2009
TERADATA US INC	16	2011–2020
CHAMDANI JOSEPH Iself	10	2012–2016
BRANSCOME JEREMY	9	2012–2016
SANERA SYSTEMS INC	7	2005–2007

Locations

Location	Patents	Span
Santa Clara, California, US	57	2000–2021
Marietta, Georgia, US	2	2000–2001