Inventor

Joseph B. Rowlands

Inventor

Santa Clara, CA, US

Overview

91→

Patents

2003–2021

Patent span

Physics

Primary field (CPC G)

Patents· 91 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing68%

H04LTransmission of digital information, e.g. telegraphic communication12%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use12%

G11CStatic stores3%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests2%

H04JMultiplex communication2%

PatentTitleYear

10,983,910Bandwidth weighting mechanism based network-on-chip (NoC) configuration2021 10,749,811Interface virtualization and fast path for Network on Chip2020 10,735,335Interface virtualization and fast path for network on chip2020 10,027,433Multiple clock domains in NoC2018 9,781,043'Identification of internal dependencies within system components for evaluating potential protocol level deadlocks'2017 9,774,498'Hierarchical asymmetric mesh with virtual routers'2017 9,563,562'Page crossing prefetches'2017 9,253,085'Hierarchical asymmetric mesh with virtual routers'2016 9,185,026'Tagging and synchronization for fairness in NOC interconnects'2015 9,130,856'Creating multiple NoC layers for isolation or avoiding NoC traffic congestion'2015 9,007,920'QoS in heterogeneous NoC by assigning weights to NoC node channels and using weighted arbitration at NoC nodes'2015 9,009,648'Automatic deadlock detection and avoidance in a system interconnect by capturing internal dependencies of IP cores using high level specification'2015 8,499,293'Symbolic renaming optimization of a trace'2013 8,370,609'Data cache rollbacks for failed speculative traces with memory operations'2013 8,370,576'Cache rollback acceleration via a bank based versioning cache ciruit'2013 8,225,315'Virtual core management'2012 8,051,247'Trace based deallocation of entries in a versioning cache circuit'2011 8,037,285'Trace unit'2011 8,032,710'System and method for ensuring coherency in trace execution'2011 8,024,522'Memory ordering queue/versioning cache circuit'2011 8,019,944'Checking for a memory ordering violation after a speculative cache write'2011 8,015,359'Method and system for utilizing a common structure for trace verification and maintaining coherency in an instruction processing circuit'2011 8,010,745'Rolling back a speculative update of a non-modifiable cache line'2011 7,991,922'System on a chip for networking'2011 7,987,342'Trace unit with a decoder, a basic-block cache, a multi-block cache, and sequencer'2011 7,966,479'Concurrent vs. low power branch prediction'2011 7,953,933'Instruction cache, decoder circuit, basic block cache circuit and multi-block cache circuit'2011 7,953,961'Trace unit with an op path from a decoder (bypass mode) and from a basic-block builder'2011 7,949,854'Trace unit with a trace builder'2011 7,941,607'Method and system for promoting traces in an instruction processing circuit'2011 7,937,564'Emit vector optimization of a trace'2011 7,934,054'Re-fetching cache memory enabling alternative operational modes'2011 7,877,630'Trace based rollback of a speculatively updated cache'2011 7,873,788'Re-fetching cache memory having coherent re-fetching'2011 7,849,292'Flag optimization of a trace'2010 7,814,298'Promoting and appending traces in an instruction processing circuit based upon a bias value'2010 7,797,563'System and method for conserving power'2010 7,779,307'Memory ordering queue tightly coupled with a versioning cache circuit'2010 7,752,281'Bridges performing remote reads and writes as uncacheable coherent operations'2010 7,663,961'Reduced-power memory with per-sector power/ground control and early address'2010 7,660,931'System on a chip for networking'2010 7,647,452'Re-fetching cache memory enabling low-power modes'2010 7,549,091'Hypertransport exception detection and processing'2009 7,469,275'System having interfaces, switch, and memory bridge for CC-NUMA operation'2008 7,443,759'Reduced-power memory with per-sector ground control'2008 7,424,561'Systems using mix of packet, coherent, and noncoherent traffic to optimize transmission between systems'2008 7,418,534'System on a chip for networking'2008 7,343,456'Load-linked/store conditional mechanism in a CC-NUMA system'2008 7,340,546'Addressing scheme supporting fixed local addressing and variable global addressing'2008 7,313,146'Transparent data format within host device supporting differing transaction types'2007 7,269,695'Ambiguous virtual channels'2007 7,266,587'System having interfaces, switch, and memory bridge for CC-NUMA operation'2007 7,228,386'Programmably disabling one or more cache entries'2007 7,206,879'Systems using mix of packet, coherent, and noncoherent traffic to optimize transmission between systems'2007 7,177,986'Direct access mode for a cache'2007 7,171,521'Coherent shared memory processing system'2007 7,131,020'Distributed copies of configuration information using token ring'2006 7,114,043'Ambiguous virtual channels'2006 7,093,052'Bus sampling on one edge of a clock signal and driving on another edge'2006 7,076,586'Default bus grant to a bus agent'2006 7,076,582'Bus precharge during a phase of a clock signal to eliminate idle clock cycle'2006 7,028,115'Source triggered transaction blocking'2006 7,003,631'System having address-based intranode coherency and data-based internode coherency'2006 7,000,076'Random generator'2006 6,993,632'Cache coherent protocol in which exclusive and modified data is transferred to requesting agent from snooping agent'2006 6,993,631'L2 cache maintaining local ownership of remote coherency blocks'2006 6,988,168'Cache programmable to partition ways to agents and/or local/remote blocks'2006 6,965,973'Remote line directory which covers subset of shareable CC-NUMA memory space'2005 6,961,824'Deterministic setting of replacement policy in a cache'2005 6,957,290'Fast arbitration scheme for a bus'2005 6,948,035'Data pend mechanism'2005 6,944,719'Scalable cache coherent distributed shared memory processing system'2005 6,941,406'System having interfaces and switch that separates coherent and packet traffic'2005 6,941,440'Addressing scheme supporting variable local addressing and variable global addressing'2005 6,918,008'Internal evict with external request'2005 6,865,633'Independent reset of arbiters and agents to allow for delayed agent reset'2005 6,848,024'Programmably disabling one or more cache entries'2005 6,816,932'Bus precharge during a phase of a clock signal to eliminate idle clock cycle'2004 6,766,389'System on a chip for networking'2004 6,748,492'Deterministic setting of replacement policy in a cache through way selection'2004 6,748,479'System having interfaces and switch that separates coherent and packet traffic'2004 6,748,495'Random generator'2004 6,745,297'Cache coherent protocol in which exclusive and modified data is transferred to requesting agent from snooping agent'2004 6,732,234'Direct access mode for a cache'2004 6,697,918'Cache configured to read evicted cache block responsive to transmitting block\'s address on interface'2004 6,684,296'Source controlled cache allocation'2004 6,678,767'Bus sampling on one edge of a clock signal and driving on another edge'2004 6,640,288'Read exclusive for fast, simple invalidate'2003 6,633,938'Independent reset of arbiters and agents to allow for delayed agent reset'2003 6,574,708'Source controlled cache allocation'2003 6,571,321'Read exclusive for fast, simple invalidate'2003

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2003–2011Patents assigned to BROADCOM CORP (51)· patent assignee history

2003–2013Based in Santa Clara, CA, US· patent location history

2010–2013Patents assigned to ORACLE AMERICA INC (24)· patent assignee history

2012–2016Patents assigned to ROWLANDS JOSEPH (6)· patent assignee history

2015–2018Patents assigned to Netspeed Systems (8)· patent assignee history

2015–2016Patents assigned to HASSAN MAHMUD (5)· patent assignee history

2015–2021Based in San Jose, CA, US· patent location history

2016–2017Based in Alviso, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
BROADCOM CORP	51	2003–2011
ORACLE AMERICA INC	24	2010–2013
Netspeed Systems	8	2015–2018
ROWLANDS JOSEPHself	6	2012–2016
HASSAN MAHMUD	5	2015–2016

Locations

Location	Patents	Span
Santa Clara, California, US	79	2003–2013
San Jose, California, US	10	2015–2021
Alviso, California, US	2	2016–2017