Inventor
Jeffrey S. Brown
Inventor
Middlesex, VT, US
Overview
Patents· 100 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices29%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1012%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1011%
G11CStatic stores9%
G06FElectric digital data processing8%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests5%
B01JChemical or physical processes, e.g. catalysis or colloid chemistry4%
H03KPulse technique3%
H10BElectronic memory devices3%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices3%
PatentTitleYear
10,662,386Method for gasifying feedstock with high yield production of biochar202010,465,133Device with dilated oxidation zone for gasifying feedstock20199,976,095Method for cleaning producer gas using a microwave induced plasma cleaning device20189,375,694'Device with dilated oxidation zone for gasifying feedstock'20169,279,090'Method for cleaning producer gas using a microwave induced plasma cleaning device'20169,150,806'Microwave induced plasma cleaning device and method for producer gas'20159,148,171'Parallel interface pattern modification for addressing signal integrity concerns'20159,064,072'Modeling semiconductor device performance'20158,829,262'Method for gasifying feedstock'20148,721,748'Device with dilated oxidation zone for gasifying feedstock'20148,667,438'Optimization of library slew ratio based circuit'20148,546,636'Method for gasifying feedstock'20138,471,720'On-chip power supply monitoring using a network of modulators'20138,432,210'Fine-grained clock skew tuning in an integrated circuit'20138,418,102'Optimization of library slew ratio based circuit'20138,336,018'Power grid optimization'20128,232,819'Closed-loop soft error rate sensitivity control'20128,196,086'Granular channel width for power optimization'20128,125,815'Transistor bit cell ROM architecture'20127,990,796'Energy efficient memory access technique for single ended bit cells'20117,966,592'Dual path static timing analysis'20117,915,571'On demand circuit function execution employing optical sensing'20117,873,921'Structure for a voltage detection circuit in an integrated circuit and method of generating a trigger flag signal'20117,872,310'Semiconductor structure and system for fabricating an integrated circuit chip'20117,847,605'Voltage detection circuit in an integrated circuit and method of generating a trigger flag signal'20107,818,695'Redistribution of current demand and reduction of power and DCAP'20107,787,325'Row decode driver gradient design in a memory device'20107,763,531'Method and structure to process thick and thin fins and variable fin to fin spacing'20107,746,722'Metal programmable self-timed memories'20107,676,716'Testable tristate bus keeper'20107,659,497'On demand circuit function execution employing optical sensing'20107,567,478'Leakage optimized memory'20097,525,864'Memory data inversion architecture for minimizing power consumption'20097,496,867'Cell library management for power optimization'20097,473,970'Concurrent fin-fet and thick body device fabrication'20097,466,171'Voltage detection circuit and circuit for generating a trigger flag signal'20087,400,543'Metal programmable self-timed memories'20087,301,210'Method and structure to process thick and thin fins and variable fin to fin spacing'20077,297,582'Method of forming high voltage N-LDMOS transistors having shallow trench isolation region with drain extensions'20077,253,066'MOSFET with decoupled halo before extension'20077,219,270'Device and method for using a lessened load to measure signal skew at the output of an integrated circuit'20077,163,851'Concurrent Fin-FET and thick-body device fabrication'20077,143,386'Type configurable memory methodology for use with metal programmable devices'20067,132,325'Test structure and methodology for semiconductor stress-induced defects and antifuse based on same test structure'20067,131,103'Conductor stack shifting'20067,087,499'Integrated antifuse structure for FINFET and CMOS devices'20067,087,486'Method for scalable, low-cost polysilicon capacitor in a planar DRAM'20067,005,334'Zero threshold voltage pFET and method of making same'20066,980,481'Address transition detect control circuit for self timed asynchronous memories'20056,963,515'Method and device for a scalable memory building block'20056,888,187'DRAM cell with enhanced SER immunity'20056,881,672'Selective silicide blocking'20056,876,035'High voltage N-LDMOS transistors having shallow trench isolation region'20056,864,136'DRAM cell with enhanced SER immunity'20056,825,530'Zero Threshold Voltage pFET and method of making same'20046,815,751'Structure for scalable, low-cost polysilicon DRAM in a planar capacitor'20046,797,592'Method for forming a retrograde implant'20046,792,578'Hard macro having an antenna rule violation free input/output ports'20046,778,449'Method and design for measuring SRAM array leakage macro (ALM)'20046,774,017'Method and structures for dual depth oxygen layers in silicon-on-insulator processes'20046,770,907'Test structure and methodology for semiconductor stress-induced defects and antifuse based on same test structure'20046,730,552'MOSFET with decoupled halo before extension'20046,700,163'Selective silicide blocking'20046,624,031'Test structure and methodology for semiconductor stress-induced defects and antifuse based on same test structure'20036,614,124'Simple 4T static ram cell for low power CMOS applications'20036,610,585'Method for forming a retrograde implant'20036,529,436'Supply degradation compensation for memory self time circuits'20036,501,695'Technique for the reduction of memory access time variation'20026,498,372'Conductive coupling of electrical structures to a semiconductor device located under a buried oxide layer'20026,486,510'Reduction of reverse short channel effects by implantation of neutral dopants'20026,476,445'Method and structures for dual depth oxygen layers in silicon-on-insulator processes'20026,429,066'Method for producing a polysilicon circuit element'20026,420,766'Transistor having raised source and drain'20026,417,070'Method for forming a liner in a trench'20026,352,912'Reduction of reverse short channel effects by deep implantation of neutral dopants'20026,301,176'Asynchronous memory self time scheme'20016,294,419'Structure and method for improved latch-up using dual depth STI with impurity implant'20016,281,593'SOI MOSFET body contact and method of fabrication'20016,255,178'Method for forming transistors with raised source and drains and device formed thereby'20016,232,639'Method and structure to reduce latch-up using edge implants'20016,232,163'Method of forming a semiconductor diode with depleted polysilicon gate structure'20016,218,704'ESD protection structure and method'20016,181,626'Self-timing circuit for semiconductor memory devices'20016,171,918'Depleted poly mosfet structure and method'20016,144,086'Structure for improved latch-up using dual depth STI with impurity implant'20006,136,656'Method to create a depleted poly MOSFET'20006,100,143'Method of making a depleted poly-silicon edged MOSFET structure'20006,097,068'Semiconductor device fabrication method and apparatus using connecting implants'20006,097,069'Method and structure for increasing the threshold voltage of a corner device'20006,057,184'Semiconductor device fabrication method using connecting implants'20006,034,388'Depleted polysilicon circuit element and method for producing the same'20006,033,949'Method and structure to reduce latch-up using edge implants'20006,015,993'Semiconductor diode with depleted polysilicon gate structure and method'20005,998,848'Depleted poly-silicon edged MOSFET structure and method'19995,981,148'Method for forming sidewall spacers using frequency doubling hybrid resist and device formed thereby'19995,976,768'Method for forming sidewall spacers using frequency doubling hybrid resist and device formed thereby'19995,939,767'Structure and process for buried diode formation in CMOS'19995,882,967'Process for buried diode formation in CMOS'19995,861,330'Method and structure to reduce latch-up using edge implants'19995,770,504'Method for increasing latch-up immunity in CMOS devices'1998Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1998–2015Patents assigned to IBM (62)· patent assignee history
1998–2001Based in Jeffersonville, VT, US· patent location history
1999–2011Based in Middlesex, VT, US· patent location history
2001–2008Patents assigned to LSI LOGIC CORP (10)· patent assignee history
2001–2015Based in Fort Collins, CO, US· patent location history
2009–2015Patents assigned to LSI CORP (18)· patent assignee history
2012–2015Patents assigned to BROWN JEFFREY S (7)· patent assignee history
2013–2019Patents assigned to PHG ENERGY LLC (8)· patent assignee history
2013–2020Based in Leland, MS, US· patent location history
2015Based in Berlin, VT, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 62 | 1998–2015 |
| LSI CORP | 18 | 2009–2015 |
| LSI LOGIC CORP | 10 | 2001–2008 |
| PHG ENERGY LLC | 8 | 2013–2019 |
| BROWN JEFFREY Sself | 7 | 2012–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Middlesex, VT, US | 50 | 1999–2011 |
| Fort Collins, CO, US | 29 | 2001–2015 |
| Jeffersonville, VT, US | 11 | 1998–2001 |
| Leland, MS, US | 9 | 2013–2020 |
| Berlin, VT, US | 1 | 2015 |