Inventor
Shigehiro Asano
Inventor
Kanagawa, JP
Overview
Patents· 92 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing60%
G11CStatic stores21%
H04LTransmission of digital information, e.g. telegraphic communication5%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use5%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h101%
A63FCard, board, or roulette games1%
B29CShaping or joining of plastics1%
B29KIndexing scheme associated with subclasses b29b, b29c or b29d, relating to moulding materials or to materials for moulds, reinforcements, fillers or preformed parts, e.g. inserts1%
B29LIndexing scheme associated with subclass b29c, relating to particular articles1%
B32BLayered products, i.e. products built-up of strata of flat or non-flat, e.g. cellular or honeycomb, form1%
PatentTitleYear
10,866,732Namespace re-sizing202010,854,302Memory system and memory control method202010,853,321Storage system202010,853,233Reconstruction of address mapping in a host of a storage system202010,845,992Semiconductor storage device with volatile and nonvolatile memories to allocate blocks to a memory and release allocated blocks202010,783,072Controller, data storage device, and program product202010,607,712Media error reporting improvements for storage drives202010,528,464Memory system and control method202010,366,003Controller, storage device, and computer program product for writing and transfer process201910,248,317Semiconductor storage device with volatile and nonvolatile memories to allocate blocks to a memory and release allocated blocks201910,229,053Controller, data storage device, and program product20199,940,233Controller, data storage device, and program product20189,703,486'Semiconductor storage device with volatile and nonvolatile memories to allocate blocks to a memory and release allocated blocks'20179,690,691'Controller, data storage device, and program product'20179,569,355'Memory system and control method'20179,324,653'Semiconductor device'20169,213,604'Semiconductor memory controlling device which writes data and error correction codes into different semiconductor storage drives'20159,165,685'Semiconductor memory device'20159,134,924'Semiconductor storage device with volatile and nonvolatile memories to allocate blocks to a memory and release allocated blocks'20159,136,020'Semiconductor memory device'20159,043,564'Memory system with fixed and variable pointers'20159,037,947'Method of controlling a semiconductor storage device'20159,009,425'Memory system with fixed and variable pointers'20158,937,844'Apparatus for generating write data and readout data'20158,812,774'Memory system and computer program product'20148,793,555'Method of controlling a semiconductor storage device'20148,788,900'Semiconductor memory device'20148,782,331'Semiconductor storage device with volatile and nonvolatile memories to allocate blocks to a memory and release allocated blocks'20148,738,867'Memory system'20148,719,615'Semiconductor device'20148,631,173'Semiconductor device'20148,612,721'Semiconductor memory controlling device'20138,611,368'Controlling bandwidth reservations method and apparatus'20138,612,824'Semiconductor memory device and controlling method'20138,611,154'Semiconductor device'20138,583,972'Method of controlling a semiconductor storage device'20138,555,027'Semiconductor memory controlling device'20138,549,388'Controller, storage apparatus, and computer program product'20138,533,560'Controller, data storage device and program product'20138,516,182'Controller and memory system for managing data'20138,495,336'Controller, data storage device, and program product'20138,483,227'Controlling bandwidth reservations method and apparatus'20138,453,033'Semiconductor memory device'20138,448,034'Semiconductor memory device'20138,438,343'Memory system with fixed and variable pointers'20138,423,709'Controller'20138,402,251'Selecting configuration memory address for execution circuit conditionally based on input address or computation result of preceding execution circuit as address'20138,397,017'Controller and data storage device'20138,392,476'Semiconductor memory device'20138,359,457'Semiconductor device and data processing method performed by semiconductor device to perform a repeat operation within a reconfigurable pipeline'20138,341,497'Semiconductor storage'20128,296,769'Order-relation analyzing apparatus, method, and computer program product thereof'20128,219,861'Semiconductor storage device'20128,195,975'Semiconductor integrated circuit device and clock control method'20128,069,301'Apparatus, storage system, and computer program product for prevention of data loss'20118,065,471'Semiconductor device having a volatile semiconductor memory and a nonvolatile semiconductor memory which performs read/write using different size data units'20118,065,470'Semiconductor storage device with volatile and nonvolatile memories'20118,065,482'Storage system and method for striping data'20118,060,797'Semiconductor storage device'20117,984,325'Storage control device, data recovery device, and storage system'20117,962,688'Semiconductor storage device with nonvolatile and volatile memories, method of controlling the same, controller and information processing apparatus'20117,953,920'Semiconductor storage device with volatile and nonvolatile memories, method of controlling the same, controller and information processing apparatus'20117,917,707'Semiconductor device'20117,818,546'Pipeline processing communicating adjacent stages and controls to prevent the address information from being overwritten'20107,793,047'Apparatus and method for generating a secondary cache index'20107,733,122'Semiconductor device'20107,721,123'Method and apparatus for managing the power consumption of a data processing system'20107,720,982'Computer architecture and software cells for broadband networks'20107,653,805'Processing in pipelined computing units with data line and circuit configuration rule signal line'20107,613,841'Systems and methods for reducing data storage in devices using multi-phase data transactions'20097,613,859'Back-off timing mechanism in a digital signal processor'20097,373,444'Systems and methods for manipulating entries in a command buffer using tag information'20087,356,713'Method and apparatus for managing the power consumption of a data processing system'20087,290,074'Back-off timing mechanism'20077,233,998'Computer architecture and software cells for broadband networks'20077,203,780'System and method for facilitating communication between devices on a bus using tags'20077,107,376'Systems and methods for bandwidth shaping'20066,820,187'Multiprocessor system and control method thereof'20046,809,734'Resource dedication system and method for a computer architecture for broadband networks'20046,735,681'Processor and branch prediction method'20046,611,870'Server device and communication connection scheme using network interface processors'20036,327,614'Network server device and file management system using cache associated with network interface processors for redirecting requested information between connection networks'20016,295,560'Data delivery system with load distribution among data delivery units using shared lower address and unique lower layer address'20016,110,547'Method of molding automobile outer trim part, laminated film or sheet for use therein and automobile outer trim part'20005,996,014'Distribution multimedia server system using shared disk arrays connected in a chain and having two ports each that are striped with digitalized video data'19995,978,875'Apparatus and method for scheduling use of bus'19995,890,189'Memory management and protection system for virtual memory in computer system'19995,862,403'Continuous data server apparatus and data transfer scheme enabling multiple simultaneous data accesses'19995,744,535'Polypropylene resin composition for exterior parts of automobile'19985,627,987'Memory management and protection system for virtual memory in computer system'19975,572,710'High speed logic simulation system using time division emulation suitable for large scale logic circuits'19965,241,641'Hierarchical cache memory apparatus'1993Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1993–2017Patents assigned to TOSHIBA KK (73)· patent assignee history
1996–2020Based in Kanagawa, JP· patent location history
1997–2020Based in Tokyo, JP· patent location history
1999–2020Based in Yokosuka, JP· patent location history
2004–2013Based in Austin, TX, US· patent location history
2011–2015Patents assigned to ASANO SHIGEHIRO (33)· patent assignee history
2011–2014Patents assigned to KANNO SHINICHI (23)· patent assignee history
2011–2014Patents assigned to FUKUTOMI KAZUHIRO (12)· patent assignee history
2012Based in Minato-ku, JP· patent location history
2018–2020Patents assigned to TOSHIBA MEMORY CORP (12)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TOSHIBA KK | 73 | 1993–2017 |
| ASANO SHIGEHIROself | 33 | 2011–2015 |
| KANNO SHINICHI | 23 | 2011–2014 |
| FUKUTOMI KAZUHIRO | 12 | 2011–2014 |
| TOSHIBA MEMORY CORP | 12 | 2018–2020 |
Locations
| Location | Patents | Span |
|---|---|---|
| Kanagawa, JP | 48 | 1996–2020 |
| Yokosuka, JP | 23 | 1999–2020 |
| Austin, Texas, US | 9 | 2004–2013 |
| Tokyo, JP | 8 | 1997–2020 |
| Minato-ku, JP | 1 | 2012 |